6402 datasheet(156/250 Pages) INTEL

156 / 250 page

Signal Lists

156

Intel® 6400/6402 Advanced Memory Buffer Datasheet

13.2

Intel 6400/6402 Advanced Memory Buffer (AMB)

Pin Description List

Table 13-3 describes the Intel 6400/6402 Advanced Memory Buffer (AMB)

packagepins.

Table 13-2. Buffer Signal Types

Buffer

Direction

Description

IInput signal

OOutput signal

AAnalog

I/O

Bidirectional (input/output) signal

Table 13-3. Pin Description (Sheet 1 of 2)

Signal

Type

Description

Channel Interface

PN[13:0]

Northbound Output Data: High speed serial signal. Read path from AMB toward host on

primary side of the DIMM connector.

PN[13:0]

Northbound Output Data Complement

SN[13:0]

Northbound Input Data: High speed serial signal. Read path from the previous AMB toward

this AMB on secondary side of the DIMM connector.

SN[13:0]

Northbound Input Data Complement

PS[9:0]

Southbound Input Data: High speed serial signal. Write path from host toward AMB on

primary side of the DIMM connector.

PS[9:0]

Southbound Input Data Complement

SS[9:0]

Southbound Output Data: High speed serial signal. Write path from this AMB toward next

AMB on secondary side of the DIMM connector. These output buffers are disabled for the last

AMB on the channel.

SS[9:0]

Southbound Output Data Complement

FBDRES

External precision resistor connected to VCC. On-die termination calibrated against this

resistor.

DRAM Interface

CB[7:0]

I/O

Check bits

DQ[63:0]

I/O

Data

DQS[17:0]

I/O

Data Strobe: DDR2 data and check-bit strobe.

DQS[17:0]

I/O

Data Strobe Complement: DDR2 data and check-bit strobe complements.

A0A-A15A,

A0B-A15B

Address: Used for providing multiplexed row and column address to SDRAM.

BA0A-BA2A,

BA0B-BA2B

Bank Active: Used to select the bank within a rank.

RASA, RASBO

Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command.

CASA, CASBO

Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command.

WEA, WEBO

Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command.

CS0A-CS1A,

CS0B-CS1B

Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are

used for selecting one of two SDRAM ranks. CS0 is used to select the first rank and CS1 is

used to select the second rank.

CKE0A-CKE1A,

CKE0B-CKE1B

Clock Enable: DIMM command register enable.

6402 Datasheet(PDF) 156 Page - Intel Corporation

6402 Datasheet(HTML) 156 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL