6402 datasheet(157/250 Pages) INTEL

157 / 250 page

Intel® 6400/6402 Advanced Memory Buffer Datasheet

157

Signal Lists

ODT0A, ODT0B

DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel.

CLK[3:0]

Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are optional and

may be disabled when not required.

CLK[3:0]

Clock Complement: Clocks to DRAMs.

DDR Compensation

DDRC_C14

DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18

DDRC_B18

DDR Compensation Ball Resistor connected to Compensation Common above

DDRC_C18

DDR Compensation Ball Resistor connected to Compensation Common above

DDRC_B12

DDR Compensation Ball Resistor connected to VSS

DDRC_C12

DDR Compensation Ball Resistor connected to VDD

Clocking

SCK

AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop

in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies required by

the core, DDR channels, and FBD Channel.

SCK

IAMB Clock Complement: This is the other differential reference clock input to the Phase

Locked Loop in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies

required by the core, DDR channels, and FBD Channel.

VCCAPLL

VCC: PLL Analog Voltage for the core PLL (See Chapter 8, Clocking)

VSSAPLL

VSS: PLL Analog Voltage for the core PLL (See Chapter 8, Clocking)

System Management

SCL

I/O

SMBus Clock

SDA

I/O

SMBus Address/Data

SA[2:0]

DIMM Select ID

Reset

RESET#

Power Good Reset

Miscellaneous Test

TEST (6 pins)

Pin for debug and test. Must be floated on DIMM.

TESTLO (3 pins)

Pin for debug and test. Must be tied to Ground on DIMM

TESTLO_AB20

Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD,

the other resistor is connected to VSS.

TESTLO_AC20

Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD,

the other resistor is connected to VSS.

Power Supplies

VCC (2pins)

1.5V nominal supply for core logic

VCCFBD (8 pins)

1.5V nominal supply for FBD high speed I/O

VDD (24 pins)

1.8V nominal supply for DDR I/O

VSS (156 pins)

Ground

VDDSPD

3.3V nominal supply for SMB receivers and ESD diodes

Other Pins

BFUNC

Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FB-DIMM. When

BFUNC = 1, AMB is used as either a repeater or a buffer for LAI function. On FB-DIMM, BFUNC

is tied to Ground

RFU (18 pins)

Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved

for forwarded clocks in future AMB implementations.

Other No Connect Pins

NC (129 pins)

No Connect pins

Table 13-3. Pin Description (Sheet 2 of 2)

Signal

Type

Description

6402 Datasheet(PDF) 157 Page - Intel Corporation

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