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MPC5606S Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc |
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MPC5606S Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 136 page  MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 113 3.20.7 Deserial Serial Peripheral Interface (DSPI) Table 62. DSPI timing1 1 DSPI timing specified at VDDE_x = 3.0 V to 5.5 V, T A = 40 to 105 °C, and CL = 50 pF with SRC = 0b11. No. Symbol C Parameter Value Unit Min Max 1tSCK CC D SCK Cycle TIme2,3 2 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. 3 The actual minimum SCK Cycle Time is limited by pad performance. 60 — ns 2tCSC CC D PCS to SCK Delay4 4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK = 2 and CSSCK = 2 20 — ns 3tASC CC D After SCK Delay5 5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC] 20 — ns 4tSDC CC D SCK Duty Cycle tSCK/2 – 2ns tSCK/2 + 2ns ns 5tA CC D Slave Access Time (PCSx active to SOUT driven) — 25 ns 6tDIS CC D Slave SOUT Disable Time (PCSx inactive to SOUT High-Z or invalid) — 25 ns 7tSUI CC D Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) 6 This delay value is corresponding to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. 35 5 5 35 — — — — ns ns ns ns 8tHI CC D Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) –4 10 26 –4 — — — — ns ns ns ns 9tSUO CC D Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) — — — — 15 35 30 15 ns ns ns ns 10 tHO CC D Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) –15 5.5 0 –15 — — — — ns ns ns ns |
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