Electronic Components Datasheet Search
  English  ▼

X  

SE98ATP Datasheet(PDF) 15 Page - NXP Semiconductors

Part # SE98ATP
Description  DDR memory module temp sensor, 1.7 V to 3.6 V
PDF  43 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SE98ATP Datasheet(HTML) 15 Page - NXP Semiconductors

Back Button SE98ATP Datasheet HTML 11Page - NXP Semiconductors SE98ATP Datasheet HTML 12Page - NXP Semiconductors SE98ATP Datasheet HTML 13Page - NXP Semiconductors SE98ATP Datasheet HTML 14Page - NXP Semiconductors SE98ATP Datasheet HTML 15Page - NXP Semiconductors SE98ATP Datasheet HTML 16Page - NXP Semiconductors SE98ATP Datasheet HTML 17Page - NXP Semiconductors SE98ATP Datasheet HTML 18Page - NXP Semiconductors SE98ATP Datasheet HTML 19Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 43 page
background image
SE98A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 November 2009
15 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.10 Hot plugging
The SE98A can be used in hot plugging applications. Internal circuitry prevents damaging
current backflow through the device when it is powered down, but with the I2C-bus,
EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and
address pins are input only) effectively places the outputs in a high-impedance state
during power-up and power-down, which prevents driver conflict and bus contention. The
50 ns noise filter will filter out any insertion glitches from the state machine, which is very
robust and not prone to false operation.
The device needs a proper power-up sequence to reset itself, not only for the device
I2C-bus and I/O initial states, but also to load specific pre-defined data or calibration data
into its operational registers. The power-up sequence should occur correctly with a fast
ramp rate and the I2C-bus active. The SE98A might not respond immediately after
power-up, but it should not damage the part if the power-up sequence is abnormal. If the
SCL line is held LOW, the part will not exit the power-on reset mode since the part is held
in reset until SCL is released.
A = ACK = Acknowledge bit. NA = Not Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 11. SMBus/I2C-bus word read from register with a pre-set pointer
123456789
D15
D14
D13
D12
D11
D10
D9
D8
returned most significant byte data
A
ACK
by host
SCL
SDA
123456789
SCL
A6
A5
A4
A3
A2
A1
A0
SDA
device address and read
RA
ACK
by device
(cont.)
(cont.)
002aab414
123456789
D7
D6
D5
D4
D3
D2
D1
D0
returned least significant byte data
P
STOP
NA
NACK
by host
S
START
by host



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com