LPC1786 datasheet(36/117 Pages) NXP

36 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

36 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[2]

I = Input; O = Output; G = Ground; S = Supply.

[3]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[4]

<tbd>

[5]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital

section of the pad is disabled.

[6]

<tbd>

[7]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[8]

Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin.

[9]

Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only).

[10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[11] <tbd>

[12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[13] <tbd>

[14] Pad provides special analog functionality.

[15] If the RTC is not used, these pins can be left floating.

[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

Table 4.

Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball

Symbol

Ball Symbol

Ball

Symbol

Ball

Symbol

Row A

P3[27]

VSS

P1[0]

P4[31]

P1[4]

P1[9]

P1[14]

P1[15]

P1[17]

P1[3]

P4[15]

VSS

P3[20]

P1[11]

P0[8]

P1[12]

P1[5]

Row B

P3[2]

P3[10]

P3[1]

P3[0]

P1[1]

VSS

P4[30]

P4[24]

P4[25]

P4[29]

P1[6]

P0[4]

VDD(3V3)

P3[19]

P4[14]

P4[13]

P2[0]

Row C

P3[13]

JTAG_TDI

P5[4]

P0[2]

P3[9]

P3[22]

P1[8]

P1[10]

9VDD(3V3)

P3[21]

P4[28]

P0[5]

P0[7]

P0[9]

P3[18]

P4[12]

VDD(3V3)-

Row D

JTAG_TRST

P3[28]

JTAG_TDO (SWO)

P3[12]

5P3[11]

P0[3]

VDD(3V3)

P3[8]

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