LPC1786 datasheet(55/117 Pages) NXP

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LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

55 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.23 I2S-bus serial I/O controllers

The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard

communication interface for digital audio applications.

The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I2S connection has one master, which is always the

master, and one slave. The I2S interface on the LPC178x/7x provides a separate transmit

and receive channel, each of which can operate as either a master or a slave.

7.23.1 Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,

48) kHz.

• Configurable word select period in master mode (separately for I2S input and output).

• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

• Controls include reset, stop and mute options separately for I2S input and I2S output.

7.24 CAN controller and acceptance filters

The LPC178x/7x contain two CAN controllers.

The Controller Area Network (CAN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its domain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router between two of CAN buses in industrial

or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words

to allow simultaneous access in the ARM environment. The main operational difference is

that the recognition of received Identifiers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

7.24.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

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