LPC1786 datasheet(40/117 Pages) NXP

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LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

40 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses are faster than the system bus and

are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for

instruction fetch (I-code) and one bus for data access (D-code). The use of two core

buses allows for simultaneous operations if concurrent operations target different devices.

Row J

RESET

RTCX1

RTCX2

P0[12]

P0[13]

P0[19]

P4[8]

P0[17]

P0[18]

VDD(3V3)

Row K

VBAT

P1[31]

P1[30]

XTAL2

P0[29]

P1[20]

P3[26]

VDD(3V3)

P4[3]

P4[6]

P0[21]

P4[7]

P4[26]

P0[20]

Row L

P2[29]

XTAL1

P0[27]

VDD(3V3)

P1[18]

P4[0]

P1[25]

VSSREG

9VSS

P0[10]

VDD(3V3)

P5[2]

VSS

P0[22]

Row M

P0[28]

P2[28]

P3[25]

P3[23]

P0[14]

P1[22]

P4[1]

P4[2]

P1[27]

P0[0]

P2[13]

P2[11]

P2[10]

P4[19]

Row N

P0[31]

USB_D-2

P3[24]

P0[30]

P2[19]

P1[21]

P1[23]

P2[21]

9VDD(REG)(3V3)

P1[29]

P0[1]

P4[16]

P4[17]/EMC_A[17]

P2[12]

Row P

P2[24]

P2[25]

P2[18]

VSS

P1[19]

P2[20]

P1[24]

P1[26]

P2[16]

P1[28]

P2[17]

P0[11]

P4[4]

P4[18]

Table 5.

Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

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