LPC1786 datasheet(63/117 Pages) NXP

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LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

63 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.33.3 Wake-up timer

The LPC178x/7x begin operation at power-up and when awakened from Power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the main oscillator or the PLL is needed by the application, software

will need to enable these features and wait for them to stabilize before they are used as a

clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code

execution. When power is applied to the chip, or when some event caused the chip to exit

Power-down mode, some time is required for the oscillator to produce a signal of sufficient

amplitude to drive the clock logic. The amount of time depends on many factors, including

the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical

characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g.,

capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.33.4 Power control

The LPC178x/7x support a variety of power control features. There are four special

modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode,

and Deep power-down mode. The CPU clock rate may also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This allows a trade-off of power versus processing speed based on application

requirements. In addition, the peripheral power control allows shutting down the clocks to

individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all

dynamic power use in any peripherals that are not required for the application. Each of the

peripherals has its own clock divider which provides even better power control.

Integrated PMU (Power Management Unit) automatically adjust internal regulators to

minimize power consumption during Sleep, Deep sleep, Power-down, and Deep

power-down modes.

The LPC178x/7x also implement a separate power domain to allow turning off power to

the bulk of the device while maintaining operation of the RTC and a small set of registers

for storing data during any of the power-down modes.

7.33.4.1

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence other than re-enabling the clock to the ARM

core.

In Sleep mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

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