LPC1786 datasheet(82/117 Pages) NXP

82 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

82 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1]

Parameters are shown as RDn or WDn in Figure 16 as indicated in the Conditions column.

[2]

Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges.

[3]

Latest of address valid, CS LOW, OE LOW, BS LOW (PB = 1).

[4]

After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid.

[5]

End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH (PB = 1).

tBLSLBLSH

BLS LOW to BLS HIGH time WR10; PB = 0

(WAITWR



WAITWEN + 1)



Tcy(clk) + <tbd>

(WAITWR



WAITWEN + 1)



Tcy(clk) + <tbd>

(WAITWR



WAITWEN + 1)



Tcy(clk) + <tbd>

tBLSHEOW

BLS HIGH to end of write

time

WR11; PB = 0 [5] <tbd>

<tbd>

tBLSHDNV

BLS HIGH to data invalid

time

WR12;

PB = 0

<tbd>

Table 15.

Dynamic characteristics: Static external memory interface …continued

CL =30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol

Parameter[1]

Conditions[1]

Min

Typ

Max

Unit

Fig 16. External static memory read/write access (PB = 0)

RD1

RD5

RD2

WR2

WR9

WR12

WR10

WR11

RD5

RD6

WR8

WR1

EOR

EOW

RD7

RD4

BLSx

002aag214

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