LPC1786 datasheet(65/117 Pages) NXP

65 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

65 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.33.4.4

Deep power-down mode

The Deep power-down mode can only be entered from the RTC block. In Deep

power-down mode, power is shut off to the entire chip with the exception of the RTC

module and the RESET pin.

To optimize power conservation, the user has the additional option of turning off or

retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn

off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the

VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before

device operation can be restarted.

The LPC178x/7x can wake up from Deep power-down mode via the RESET pin or an

alarm match event of the RTC.

7.33.4.5

Wake-up Interrupt Controller (WIC)

The WIC allows the CPU to automatically wake up from any enabled priority interrupt that

can occur while the clocks are stopped in Deep sleep, Power-down, and Deep

power-down modes.

The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When

the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a

mask of the current interrupt situation to the WIC.This mask includes all of the interrupts

that are both enabled and of sufficient priority to be serviced immediately. With this

information, the WIC simply notices when one of the interrupts has occurred and then it

wakes up the CPU.

The WIC eliminates the need to periodically wake up the CPU and poll the interrupts

resulting in additional power savings.

7.33.5 Peripheral power control

A power control for peripherals feature allows individual peripherals to be turned off if they

are not needed in the application, resulting in additional power savings.

7.33.6 Power domains

The LPC178x/7x provide two independent power domains that allow the bulk of the

device to have power removed while maintaining operation of the RTC and the backup

registers.

On the LPC178x/7x, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the

VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the

CPU and most of the peripherals.

Depending on the LPC178x/7x application, a design can use two power options to

manage power consumption.

The first option assumes that power consumption is not a concern and the design ties the

VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

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