AM3871 datasheet(223/345 Pages) TI1

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EMQAC[x]_RGTXC

(at DSP)

(A)

EMAC[x]_RGTXD[3:0]

(B)

EMAC[x]_RGTXCTL

(B)

1st Half-byte

TXERR

TXEN

2nd Half-byte

Internal RGTXC

RGTXC at DSP pins

AM3874, AM3872, AM3871

www.ti.com

SPRS695

– SEPTEMBER 2011

Table 8-24. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII

Transmit(1)

(see Figure 8-17)

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

Internal delay enabled

1.2

tsu(RGTXD-

Setup time, transmit selected signals valid before

RGTXCH)

EMAC[x]_RGTXC (at DSP) high/low

Internal delay disabled

-0.5

Internal delay enabled

1.2

th(RGTXCH-

Hold time, transmit selected signals valid after

RGTXD)

EMAC[x]_RGTXC (at DSP) high/low

Internal delay disabled

-0.5

(1)

For RGMII, transmit selected signals include: EMAC[x]_RGTXD[3:0] and EMAC[x]_RGTXCTL.

RGTXC is delayed internally before being driven to the EMAC[x]_RGTXC pin. The internal delay can be enabled or

disabled via the EMAC RGMII_ID_MODE_N register.

Data and control information is transmitted using both edges of the clocks. EMAC[x]_RGTXD[3:0] carries data bits 3-0

on the rising edge of EMAC[x]_RGTXC and data bits 7-4 on the falling edge of EMAC[x]_RGTXC. Similarly,

EMAC[x]_RGTXCTL carries TXEN on rising edge of EMAC[x]_RGTXC and TXERR of falling edge of

EMAC[x]_RGTXC.

Figure 8-17. EMAC Transmit Interface Timing [RGMII Operation]

Peripheral Information and Timings

223

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