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ACS32201 Datasheet(PDF) 35 Page - Integrated Device Technology |
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ACS32201 Datasheet(HTML) 35 Page - Integrated Device Technology |
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35 / 65 page  IDT CONFIDENTIAL 30 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER • PWM Control 0 Register • PWM Control 1 Register • PWM Control 2 Register • PWM Control 3 Register Register Address Bit Label Type Default Description R66 (42h) PWM0 7:5 SCTO RW 11 Class-D Short Circuit Detect Time-out 00 = 10uS 01 = 100uS 10 = 500uS 11 = 100mS 5UVLO RW 1 Under Voltage Lock Out 1 = BTL output disabled if PVDD sense circuit returns code 0 4 roundup RW 1 1 = roundup, 0 = truncate for quantizer 3 bfclr RW 0 1 = disable binomial filter 2 fourthorder RW 1 1 = 4th order binomial filter; 0 = 3rd order 1 add3_sel RW 0 1 = 24-bit Noise Shaper output (pre-quantizer) 0 = 8/9/10-bit quantizer output 0 quantizer_sel RW 0 Table 42. PWM0 Register Register Address Bit Label Type Default Description R67 (43h) PWM1 7 RSVD R 0 Reserved 6:2 dithpos[4:0] RW 0 Dither position, where dither inserted after NS. 0,1,2 = dither bits 2:0 4 = dither bits 3:1 5 = dither bits 4:1 .... 19 = dither bits 19:17 1 dith_range RW 0 1 = dither -1 to +1, 0 = -3 to +3 0 dithclr RW 0 1 = disable dither Table 43. PWM1 Register Register Address Bit Label Type Default Description R68 (44h) PWM2 7:2 dvalue[5:0] RW 18h dvalue constant field 1 pwm_outflip RW 0 1 = swap pwm a/b output pair for all channels The control lines to the power stage are swapped inverting the output signal. 0 pwm_outmode RW 1 1 = tristate, 0 = binary Table 44. PWM2 Register Register Address Bit Label Type Default Description R69 (45h) PWM3 7:6 outctrl[1:0] RW 00 pwm output muxing 0 = normal 1 = swap 0/1 2 = ch0 on both 3 = ch1 on both 5:0 cvalue[5:0] RW 0Ah tristate constant field, must be even and not 0 Table 45. PWM3 Register |
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