ACS32201 datasheet(13/65 Pages) IDT

13 / 65 page

IDT CONFIDENTIAL

V0.6 07/11

ACS32201

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

•

DACCRAM Read Data (0x3D–LO, 0x3E–MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI)

Registers

These two 24-bit registers provide the 24-bit data holding registers used when doing indirect writes/reads to the DAC

Coefficient RAM.

•

DACCRAM Address Register

This 7-bit register provides the address to the internal RAM when doing indirect writes/reads to the DAC Coefficient

RAM.

•

DACCRAM STATUS Register

This control register provides the write/read enable when doing indirect writes/reads to the DAC Coefficient RAM.

Bit

Label

Type

Default

Description

R58 (3Ah)

DACCRAM_WRITE_LO

7:0

DACCRWD[7:0]

R/W

Low byte of a 24-bit data register, contains the values

to be written to the DACCRAM. The address written will

have been specified by the DACCRAM Address fields.

R59 (3Bh)

DACCRAM_WRITE_MID

7:0

DACCRWD[15:8]

R/W

Middle byte of a 24-bit data register, contains the

values to be written to the DACCRAM. The address

written will have been specified by the DACCRAM

Address fields.

R60 (3Ch)

DACCRAM_WRITE_HI

7:0

DACCRWD[23:16]

R/W

High byte of a 24-bit data register, contains the values

to be written to the DACCRAM. The address written will

have been specified by the DACCRAM Address fields.

R61 (3Dh)

DACCRAM_READ_LO

7:0

DACCRRD[7:0]

Low byte of a 24-bit data register, contains the contents

of the most recent DACCRAM address read from the

RAM. The address read will have been specified by the

DACCRAM Address fields.

R62 (3Eh)

DACCRAM_READ_MID

7:0

DACCRRD[15:8]

Middle byte of a 24-bit data register, contains the

contents of the most recent DACCRAM address read

from the RAM. The address read will have been

specified by the DACCRAM Address fields.

R63 (3Fh)

DACCRAM_READ_HI

7:0

DACCRRD[23:16]

High byte of a 24-bit data register, contains the

contents of the most recent DACCRAM address read

from the RAM. The address read will have been

specified by the DACCRAM Address fields.

Table 10. DACCRAM Read/Write Registers

Bit

Label

Type

Default

Description

R64 (40h)

DACCRADDR

7:0

DACCRADD

R/W

Contains the address (between 0 and 255) of the

DACCRAM to be accessed by a read or write. This is

not a byte address--it is the address of the 24-bit

data item to be accessed from the DACCRAM.This

address is automatically incremented after writing to

DACCRAM_WRITE_HI or reading from

DACCRAM_READ_HI (and the 24 bit data from the

next RAM location is fetched.)

Table 11. DACCRAM Address Register

Bit

Label

Type

Default

Description

R138 (8Ah)

DACCRSTAT

DACCRAM_Busy

1 = read/write to DACCRAM in progress, cleared by

HW when done.

6:0

RSVD

Reserved

Table 12. DACCRAM Status Register

ACS32201 Datasheet(PDF) 13 Page - Integrated Device Technology

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