ACS32201 datasheet(49/65 Pages) IDT

49 / 65 page

IDT CONFIDENTIAL

V0.6 07/11

ACS32201

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

5. AUDIO CLOCK GENERATION

5.1.

Internal Clock Generation

The PLL block provides two clocks for the audio portion of the device. They are

•

122.880 MHz (2560 x 48 KHz)

•

112.896 (2560 x 44.1 KHz)

It is important that the crystal oscillator and needed PLLs remain on until all audio functions are dis-

abled.

5.2.

Clocking and Sample Rates

The ACS32201 utilizes internal PLLs to generate the audio master clock (MCLK) at 56.448MHz (22.5792MHz *2.5)

and 61.44MHz (24.576 *2.5). It then generates audio sample rates directly from the master clock. After changing rate,

a delay of up to 5mS may be needed for the part to properly lock PLLs, flush filters, etc.

The clocking of the ACS32201 is controlled using the BR[1:0] and BM[2:0] control bits. Each value of

BR[1:0] + BM[2:0]selects one combination of MCLK division ratios and hence one combination of

sample rates

The BR[1:0] and BM[2:0] bits must be set to configure the appropriate ADC and DAC sample rates in

both master and slave mode.

Bit

Label

Type

Default

Description

R25 (19h)

DAC Sample Rate

Control

(DACSR)

7:6

DBCM[1:0]

DAC Bit Clock Mode (for data interface DACBCLK

generation in master mode)

00 = Auto

01 = 32x fs

10 = 40x fs

11 = 64x fs

RSVD

Reserved

4:3

DBR[1:0]

DAC Base Rate

00 = 32KHz

01 = 44.1KHz

10 = 48KHz

11 = Reserved

2:0

DBM[2:0]

010

DAC Base Rate Multiplier

000 = 0.25x

001 = 0.50x

010 = 1x

011 = 2x

100-111 = Reserved

Table 61. DACSR Register

BR [1:0]

BM [2:0]

MCLK

SAMPLE RATE

000

40.96 MHz

8 kHz (MCLK/5120)

001

16 kHz (MCLK/2560)

010

32 kHz (MCLK/1280)

011

Reserved

100-111

Reserved

Table 62. Master Clock and Sample Rates

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