ACS32201 datasheet(8/65 Pages) IDT

8 / 65 page

IDT CONFIDENTIAL

V0.6 07/11

ACS32201

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

2. POWER MANAGEMENT

2.1.

Control Registers

The ACS32201 has control registers to enable system software to control which functions are active. To minimize

power consumption, unused functions should be disabled. To avoid audio artifacts, it is important to enable or disable

functions in the correct order.

2.2.

Stopping the Master Clock

In order to minimize digital core power consumption, the master clock may be stopped in Standby and OFF modes by

setting the DIGENB bit (R25, bit 0).

Note: Before DIGENB can be set, the control bits SPKL and SPKR must be set to zero and a

waiting time of 100ms must be observed to allow port ramping/gain fading to complete. Any failure

to follow this procedure may cause pops or, if less than 1mS, may prevent the DACs from

re-starting correctly.

Bit

Label

Type

Default

Description

0x1A

Power Management 1

7:1

RSVD

Reserved

0DIGENB

Master clock disable

0: master clock enabled, 1: master clock disabled

Table 1. Power Management Register 1

Bit

Label

Type

Default

Description

0x1B

Power Management 2

7:5

RSVD

Reserved

SPKL

LSPK Output Buffer

0 = Power down, 1 = Power up

SPKR

RSPK Output Buffer

0 = Power down, 1 = Power up

2:1

RSVD

Reserved

0VREF

VREF (necessary for all other functions)

0 = Power down, 1 = Power up

Table 2. Power Management Register 2

Bit

Label

Type

Default

Description

0x1A

Power Management 1

0DIGENB

Master clock disable

0 = master clock enabled, 1 = master clock disabled

Table 3. Power Management Register1 -- Master Clock Disable

ACS32201 Datasheet(PDF) 8 Page - Integrated Device Technology

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