ACS32201 datasheet(6/65 Pages) IDT

6 / 65 page

IDT CONFIDENTIAL

V0.8 04/11

ACS422X68

ACS422x68

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

LIST OF FIGURES

Figure 1. ACS32201 Block Diagram ................................................................................................................2

Figure 2. Output Audio Processing ..................................................................................................................4

Figure 3. Prescaler & EQ Filters ......................................................................................................................6

Figure 4. 6-Tap IIR Equalizer Filter ..................................................................................................................7

Figure 5. DAC Coefficient RAM Write Sequence .............................................................................................9

Figure 6. DAC Coefficient RAM Read Sequence ...........................................................................................10

Figure 7. Gain Compressor, Output vs Input .................................................................................................13

Figure 8. Compressor block diagram .............................................................................................................15

Figure 9. 3-D Channel Inversion ....................................................................................................................20

Figure 10. Bass Enhancement .......................................................................................................................21

Figure 11. Treble Enhancement ....................................................................................................................23

Figure 12. Constant Output Power Error ........................................................................................................27

Figure 13. Constant Output Power nominal and high/low ..............................................................................28

Figure 14. Temp sense volume adjustment algorithm ...................................................................................34

Figure 15. Master mode .................................................................................................................................37

Figure 16. Slave mode ...................................................................................................................................37

Figure 17. Left Justified Audio Interface (assuming n-bit word length) ..........................................................38

Figure 18. Right Justified Audio Interface (assuming n-bit word length) ........................................................38

Figure 19. I2S Justified Audio Interface (assuming n-bit word length) ...........................................................39

Figure 20. Bit Clock mode ..............................................................................................................................41

Figure 21. 2-Wire Serial Control Interface ......................................................................................................41

Figure 22. Multiple Write Cycle ......................................................................................................................42

Figure 23. Read Cycle ...................................................................................................................................42

Figure 24. Multiple Read Cycle ......................................................................................................................43

Figure 25. ACS32201 TAG Pinout .................................................................................................................51

Figure 26. ACS32201 NAG Pinout ................................................................................................................52

Figure 27. Package Outline ...........................................................................................................................57

Figure 28. NAG/HLA Package Outline ...........................................................................................................58

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