ACS32201 datasheet(45/65 Pages) IDT

45 / 65 page

IDT CONFIDENTIAL

V0.6 07/11

ACS32201

LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER

4.7.2.

Audio Interface Output Tri-state

TRI is used to tri-state the DACLRCK and DACBCLK pins. In Slave mode (MASTER=0) all pins are configured as

inputs. The Tri-stated pins are pulled low with an internal pull-down resistor unless that resistor is disabled.

4.7.3.

Audio Interface Control 3 Register

4.8.

Bit Clock Mode

The default master mode bit clock generator automatically produces a bit clock frequency based on the sample rate

and word length. When enabled by setting the appropriate BCM bits, the bit clock mode (BCM) function overrides the

default master mode bit clock generator to produce the bit clock frequency shown below: Note that selecting a word

length of 24-bits in Auto mode generates 64 clocks per frame (64fs)

The BCM mode bit clock generator produces 16, 20, or 32 bit cycles per sample.

Bit

Label

Type

Default

Description

R20 (14h)

Audio Interface

Control 2

(AIC2)

7:6

DACDSEL[1:0]

00: left DAC = left I2S data; right DAC = right I2S data

01: left DAC = left I2S data; right DAC = left I2S data

10: left DAC = right I2S data; right DAC = right I2S data

11: left DAC = right I2S data; right DAC = left I2S data

5:4

RSVD

Reserved

3TRI

Tri-states DACLRCLK and DACBCLK pins.

0 = DACLRCLK and DACBCLK are inputs (slave mode)

or outputs (master mode)

1 = DACLRCLK and DACBCLK are high impedance

2:0

BLRCM[2:0]

000

Bitclock and LRClock mode. See Table Below

Table 54. AIC2 Register

Bit

Label

Type

Default

Description

R21 (15h)

Audio Interface

Control 3

(AIC3)

7:3

RSVD

Reserved

DDIPDD

DACDIN Pull-Down Disable

0 = Pull-Down active

1 = Pull-Down always disabled

1DLRPDD

DACLRCLK Pull-Down Disable

0 = Pull-Down active when configured as input

1 = Pull-Down always disabled

DBCPDD

DACBCLK Pull-Down Disable

0 = Pull-Down active when configured as input

1 = Pull-Down always disabled

Table 55. AIC3 Register

Bit

Label

Type

Default

Description

R25 (17h/19h

DAC Sample Rate

Control

7:6

DBCM[1:0]

BCLK Frequency

00 = Auto

01 = 32 x fs

10 = 40 x fs

11 = 64 x fs

Table 56. Master Mode BCLK Frequency Control Register

ACS32201 Datasheet(PDF) 45 Page - Integrated Device Technology

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