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ACS32201 Datasheet(PDF) 10 Page - Integrated Device Technology |
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ACS32201 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 65 page ![]() IDT CONFIDENTIAL 5 V0.6 07/11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS32201 ACS32201 LOW-POWER, HIGH-FIDELITY, CLASS-D AMPLIFIER 3.2. Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The level of attenuation is specified by an eight-bit code, ‘DACVOL_x’, where ‘x’ is L, or R. The value “00000000” indi- cates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. The Volume Update bits control the updating of volume control data; when a bit is written as ‘0’, the Left Volume control associated with that bit is updated whenever the left volume register is written and the Right Volume control is updated when ever the right volume register is written. When a bit is written as ‘1’, the left volume data is placed into an internal holding register when the left volume register is written and both the left and right volumes are updated when the right volume register is written. This enables a simultaneous left and right volume update The output path may be muted automatically when a long string of zero data is received. The length of zeros is pro- grammable and a detection flag indicates when a stream of zero data has been detected. Register Address Bit Label Type Default Description R10 (0Ah) VUCTL 7 RSVD RW 1 Reserved 6 DACFade RW 1 1 = volume fades between old/new value 0 = volume/mute changes immediately 5:3 RSVD R 0 Reserved for future use. 2 DACVOLU RW 0 0 = Left DAC volume updated immediately 1 = Left DAC volume held until right DAC volume register written. 1 SPKVOLU RW 0 0 = Left speaker volume updated immediately 1 = Left speaker volume held until right speaker volume register written. 0 RSVD RW 0 Reserved Table 6. Volume Update Control Register Register Address Bit Label Type Default Description R33 (21h) Gain Control (GAINCTL) 7 zerodet_flag R 0 1 = zero detect length exceeded. 6 RSVD R 0 Reserved for future use. 5:4 zerodetlen RW 2 Enable mute if input consecutive zeros exceeds this length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples 3 RSVD R 0 Reserved for future use. 2 auto_mute RW 1 1 = auto mute if detect long string of zeros on input 1 RSVD R 0 Reserved for future use. 0 RSVD R 0 Reserved for future use. 7 zerodet_flag R 0 1 = zero detect length exceeded. Table 7. Gain Control Register |
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