ADS4128 datasheet(13/61 Pages) TI

13 / 61 page

Dn_Dn+1_P

Dn_Dn+1_M

GND

Logic0

ODL

Logic1

ODH

OCM

ADS4128

www.ti.com

SBAS578 – MAY 2012

TIMING CHARACTERISTICS

(1) With external 100-

Ω termination.

Figure 4. LVDS Output Voltage Levels

TIMING REQUIREMENTS: LVDS and CMOS Modes

(1)

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock,

CLOAD = 5 pF

(2), and R

LOAD = 100 Ω

(3), unless otherwise noted. Minimum and maximum values are across the full temperature

range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

0.6

0.8

1.2

Between two devices at the same temperature and DRVDD

Aperture delay variation

±100

supply

Aperture jitter

100

fS rms

Time to valid data after coming out of STANDBY mode

µs

Wakeup time

Time to valid data after coming out of PDN GLOBAL mode

100

500

µs

Clock

Low-latency mode (default after reset)

cycles

Low-latency mode disabled

Clock

ADC latency(4)

(gain enabled, offset correction disabled)

cycles

Low-latency mode disabled

Clock

(gain and offset correction enabled)

cycles

DDR LVDS MODE(5)(6)

tSU

Data setup time(3)

Data valid(7) to zero-crossing of CLKOUTP

1.05

1.55

Data hold time(3)

Zero-crossing of CLKOUTP to data becoming invalid(7)

0.35

0.6

Input clock rising edge crossover to output clock rising edge

tPDI

Clock propagation delay

crossover

4.2

5.4

1 MSPS ≤ sampling frequency ≤ 200 MSPS

Between two devices at the same temperature and DRVDD

Variation of tPDI

±0.6

supply

(1)

Timing parameters are ensured by design and characterization but are not production tested.

(2)

CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(3)

RLOAD is the differential load resistance between the LVDS output pair.

(4)

At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.

(5)

Measurements are done with a transmission line of 100-

Ω characteristic impedance between the device and the load. Setup and hold

time specifications take into account the effect of jitter on the output data and clock.

(6)

The LVDS timings are unchanged for low latency disabled and enabled.

(7)

Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V.

Submit Documentation Feedback

Product Folder Link(s): ADS4128

ADS4128 Datasheet(PDF) 13 Page - Texas Instruments

ADS4128 Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL