ADS4128 datasheet(24/61 Pages) TI

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ADS4128

SBAS578 – MAY 2012

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GAIN

DISABLE GAIN

TEST PATTERNS

Bits[7:4]

GAIN: Gain programmability

These bits set the gain programmability in 0.5-dB steps.

0000 = 0-dB gain (default after reset)

0111 = 3.5-dB gain

0001 = 0.5-dB gain

1000 = 4.0-dB gain

0010 = 1.0-dB gain

1001 = 4.5-dB gain

0011 = 1.5-dB gain

1010 = 5.0-dB gain

0100 = 2.0-dB gain

1011 = 5.5-dB gain

0101 = 2.5-dB gain

1100 = 6.0-dB gain

0110 = 3.0-dB gain

Bit 3

DISABLE GAIN: Gain setting

This bit sets the gain.

0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled

1 = Gain disabled

Bits[2:0]

TEST PATTERNS: Data capture

These bits verify data capture.

000 = Normal operation

001 = Outputs all '0's

010 = Outputs all '1's

011 = Outputs toggle pattern

Output data D[11:0] is an alternating sequence of 010101010101 and 101010101010.

100 = Outputs digital ramp

Output data increments by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095

101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern)

110 = Unused

111 = Unused

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