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ADS4128 Datasheet(PDF) 30 Page - Texas Instruments |
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ADS4128 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 61 page ![]() ADS4128 SBAS578 – MAY 2012 www.ti.com Register Address CFh (Default = 00h) 7 6 5 4 3 2 1 0 FREEZE BYPASS OFFSET OFFSET OFFSET CORR TIME CONSTANT 0 0 CORR CORR Bit 7 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set) 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the last estimated value is used for offset correction every clock cycle. See OFFSET CORRECTION, Offset Correction. Bit 6 Always write '0' Bits[5:2] OFFSET CORR TIME CONSTANT These bits set the offset correction time constant for the correction loop time constant in number of clock cycles. VALUE TIME CONSTANT (Number of Clock Cycles) 0000 1 M 0001 2 M 0010 4 M 0011 8 M 0100 16 M 0101 32 M 0110 64 M 0111 128 M 1000 256 M 1001 512 M 1010 1 G 1011 2 G Bits[1:0] Always write '0' Register Address DFh (Default = 00h) 7 6 5 4 3 2 1 0 0 0 LOW SPEED 0 0 0 0 Bits[7:1] Always write '0' Bit 0 LOW SPEED: Low-speed mode 00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80 MSPS. 11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal to 80 MSPS. 30 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS4128 |
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