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ADS4128 Datasheet(PDF) 25 Page - Texas Instruments

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Part # ADS4128
Description  12-Bit, 200-MSPS, Ultralow-Power ADC
PDF  61 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS4128 Datasheet(HTML) 25 Page - Texas Instruments

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ADS4128
www.ti.com
SBAS578 – MAY 2012
Register Address 26h (Default = 00h)
7
6
5
4
3
2
1
0
LVDS CLKOUT
LVDS DATA
0
0
0
0
0
0
STRENGTH
STRENGTH
Bits[7:2]
Always write '0'
Bit 1
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100-
Ω external termination (default strength)
1 = 50-
Ω external termination (2x strength)
Bit 0
LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100-
Ω external termination (default strength)
1 = 50-
Ω external termination (2x strength)
Register Address 3Dh (Default = 00h)
7
6
5
4
3
2
1
0
EN OFFSET
DATA FORMAT
0
0
0
0
0
CORR
Bits[7:6]
DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
PATTERN D11
PATTERN D10
PATTERN D9
PATTERN D8
PATTERN D7
PATTERN D6
PATTERN D5
PATTERN D4
Bits[7:0]
CUSTOM PATTERN
These bits set the custom pattern.
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
0
0
0
0
PATTERN D3
PATTERN D2
PATTERN D1
PATTERN D0
Bits[7:2]
CUSTOM PATTERN
These bits set the custom pattern.
Bits[3:0]
Always write '0'
Copyright © 2012, Texas Instruments Incorporated
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