ADS4128 datasheet(19/61 Pages) TI

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SCLK

DSU

SLOADS

SLOADH

SDATA

SCLK

SEN

RESET

RegisterAddress

RegisterData

ADS4128

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SBAS578 – MAY 2012

SERIAL INTERFACE

The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface

formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)

pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every

SCLK falling edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK

falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data

can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register

address and the remaining eight bits are the register data. The interface can function with an SCLK frequency

from 20 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to default values. This initialization can be accomplished

in one of two ways:

1. Either through hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns), as

shown in Figure 9; or

2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.

This setting initializes the internal registers to default values and then self-resets the RESET bit low. In this

case, the RESET pin is kept low.

Figure 9. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

Typical values are at +25°C, minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX =

+85°C, AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted.

PARAMETER

MIN

TYP

MAX

UNIT

fSCLK

SCLK frequency (equal to 1/tSCLK)

> dc

MHz

tSLOADS

SEN to SCLK setup time

tSLOADH

SCLK to SEN hold time

tDSU

SDATA setup time

tDH

SDATA hold time

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