ADS4128 datasheet(16/61 Pages) TI

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N+1

N+2

InputClock

CLKOUTM

CLKOUTP

OutputData

(2)

(DXP,DXM)

DDRLVDS

N+1

CLKOUT

OutputData

ParallelCMOS

InputSignal

SampleN

N+1

N+2

N+3

N+4

N+10

N+11

N+12

PDI

CLKP

CLKM

10ClockCycles

(1)

10ClockCycles

(1)

ADS4128

SBAS578 – MAY 2012

www.ti.com

Table 7. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)

TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK

tSTART (ns)

tDV (ns)

SAMPLING FREQUENCY

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

200

—

0.3

3.5

4.2

—

185

—

3.9

4.5

—

170

—

–1.3

4.3

—

(1) ADC latency in low-latency mode. At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall

latency = ADC latency + 1.

(2) E = Even bits (D0, D2, D4, and so on). O = Odd bits (D1, D3, D5, and so on).

Figure 5. Latency Diagram

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