ADS4128 datasheet(27/61 Pages) TI

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ADS4128

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SBAS578 – MAY 2012

DIS LOW

CLKOUT FALL CTRL

STBY

LATENCY

Bits[7:6]

CLKOUT FALL CTRL

Controls position of output clock falling edge

LVDS interface:

00 = Default position (timings are specified in this condition)

01 = Setup reduces by 400 ps, hold increases by 400 ps

10 = Data transition is aligned with rising edge

11 = Setup reduces by 200 ps, hold increases by 200 ps

CMOS interface:

00 = Default position (timings are specified in this condition)

01 = Falling edge is advanced by 100 ps

10 = Falling edge is advanced by 200 ps

11 = Falling edge is advanced by 1.5 ns

Bits[5:4]

Always write '0'

Bit 3

DIS LOW LATENCY: Disable low latency

This bit disables low-latency mode.

0 = Low-latency mode is enabled. Digital functions such as gain, test patterns, and offset correction

are disabled.

1 = Low-latency mode is disabled. This setting enables the digital functions. See the Digital

Functions and Low-Latency Mode section.

Bit 2

STBY: Standby mode

This bit sets the standby mode.

0 = Normal operation

1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time

from standby is fast

Bits[1:0]

Always write '0'

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ADS4128 Datasheet(PDF) 27 Page - Texas Instruments