TAS3202 datasheet(18/66 Pages) TI1

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TAS3202

SLES208B – JUNE 2009 – REVISED MARCH 2011

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Clock Controls

Clock management for the TAS3202 consists of two control structures:

•

Master clock management

–

Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and

the audio DSP core

–

The master clock (MCLK_IN or XTAL_IN) is the source for these clocks.

–

In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the

DPLL output drives the microprocessor and audio DSP clocks.

–

Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the

microprocessor and audio DSP clocks.

•

Serial audio port (SAP) clock management

–

Oversees SAP master/slave mode

–

Controls output of SCLKOUT, and LRCLK in the SAP master mode

Input pin MCLK_IN or XTAL_IN provides the master clock for the TAS3202. Within the TAS3202, these

two inputs are combined by an OR gate and, thus, only one of these two sources can be active at any one

time. The source that is not active must be logic 0.

The TAS3202 only supports dynamic sample-rate changes between any of the supported sample

frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the

TAS3202 remains in normal operation and the register contents are preserved. To avoid producing audio

artifacts during the sample-rate changes, a volume or mute control can be included in the application

firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be

provided by a crystal attached to XTAL_IN and XTAL_OUT or an external 3.3-V fixed-frequency TTL

source attached to MCLK_IN.

When the TAS3202 is used in a system in which the master clock frequency (fMCLK ) can change, the

TAS3202 must be reset during the frequency change. In these cases, the procedure shown in Figure 5-1

should be used.

Clock Controls

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