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TAS3202 Datasheet(PDF) 14 Page - Texas Instruments |
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TAS3202 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 66 page  23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelLeft-JustifiedStereoInput T0034-02 4 5 9 8 1 4 5 1 0 0 0 23 22 1 19 18 15 14 MSB LSB 4 5 9 8 1 4 5 1 0 0 0 SCLK TAS3202 SLES208B – JUNE 2009 – REVISED MARCH 2011 www.ti.com 3.9.2 2-Channel Left-Justified Timing In 2-channel left-justified timing, LRCLK is HIGH when left-channel data is transmitted and LOW when right-channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS3202 masks unused trailing data-bit positions. Figure 3-3. Left-Justified 64fS Format 14 Physical Characteristics Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3202 |
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