TAS3202 datasheet(20/66 Pages) TI1

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SDA

SCL

Start

(By Master)

Slave Address

(By Master)

Read or Write

(By Master)

Acknowledge

(By TAS3202)

Data Byte

(By Transmitter)

Acknowledge

(By Receiver)

Data Byte

(By Transmitter)

Acknowledge

(By Receiver)

Stop

(By Master)

MSB

MSB-1 MSB-2

LSB

Start Condition

SDA ↓While SCL = 1

Stop Condition

SDA ↑While SCL = 1

(1)

TAS3202

SLES208B – JUNE 2009 – REVISED MARCH 2011

www.ti.com

Microprocessor Controller

The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus

controllers the required I2C read data, and participates in most processing tasks requiring multiframe

processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing

I2C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program

cannot be altered. The microprocessor controller has specialized hardware for I2C master and slave

interface operation, volume updates, and a programmable interval timer interrupt.

The TAS3202 has a slave-only I2C interface that is compatible with the Inter IC (I2C) bus protocol and

supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read operations

(maximum is 20 bytes). The slave I2C control interface is used to program the registers of the device and

to read device status.

The TAS3202 also has a master-only I2C interface that is compatible with the I2C bus protocol and

supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes).

The master I2C interface is used to load program and data from an external I2C EEPROM.

Once the microprocessor program memory has been loaded, it cannot be updated until the TAS3202 has

been reset.

The master and slave I2C ports do not operate simultaneously.

When acting as an I2C master, the data transfer rate is fixed at 375 kHz, assuming MCLK_IN or

XTAL_IN = 24.576 MHz.

When acting as an I2C slave, the data transfer rate is determined by the I2C master device on the bus.

The I2C communication protocol for the I2C slave mode is shown in Figure 6-1.

Figure 6-1. I2C Slave-Mode Communication Protocol

6.1

8051 Microprocessor Addressing Mode

The 256 bytes of internal data memory address space is accessible using indirect addressing instructions

(including stack operations). However, only the lower 128 bytes are accessible using direct addressing.

The upper 128 bytes of direct address Data Memory space are used to access Extended Special Function

Registers (ESFRs).

Microprocessor Controller

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