TAS3202 datasheet(43/66 Pages) TI1

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TAS3202

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SLES208B – JUNE 2009 – REVISED MARCH 2011

8.10 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I

2C-Bus

Devices

STANDARD

FAST

MODE

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

VIL

LOW-level input voltage

–0.5

0.8

–0.5

0.8

VIH

HIGH-level input voltage

Vhys

Hysteresis of inputs

N/A

0.05 VDD

LOW-level output voltage (open drain

VOL1

3-mA sink current

0.4

or open collector)

Bus capacitance from 10 pF

7 + 0.1 Cb

tof

Output fall time from VIHmin to VILmax

250

to 400 pF

(1)

Input current, each I/O pin

–10

–10(2)

10(2)

μA

SCL pulse duration of spikes that must

tSP(SCL)

N/A

14(3)

be suppressed by the input filter

SDA pulse duration of spikes that must

tSP(SDA)

N/A

22(3)

be suppressed by the input filter

Capacitance, each I/O pin

(1)

Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I

2C specification.

(2)

The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.

(3)

These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by half, the tSP doubles.

8.11 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I

2C-Bus

Devices

all values are referred to VIHmin and VILmax (see Section 8.10)

STANDARD MODE

FAST MODE

PARAMETER

UNIT

MIN

MAX

MIN

MAX

fSCL

SCL clock frequency

100

400(1)

kHz

Hold time (repeated) START condition. After this period, the first

tHD-STA

0.6

μs

clock pulse is generated.

tLOW

LOW period of the SCL clock

4.7

1.3

μs

tHIGH

HIGH period of the SCL clock

0.6

μs

tSU-STA

Setup time for repeated START

4.7

0.6

μs

tSU-DAT

Data setup time

250

100

μs

tHD-DAT

Data hold time (2) (3)

3.45

0.9

μs

Rise time of both SDA and SCL signals

1000

20 + 0.1 Cb

(4)

300

Fall time of both SDA and SCL

300

20 + 0.1 Cb

(4)

300

tSU-STO

Setup time for STOP condition

0.6

μs

tBUF

Bus free time between a STOP and START condition

4.7

1.3

μs

Capacitive load for each bus line

400

Noise margin at the LOW level for each connected device

VnL

0.1VDVDD

(including hysteresis)

Noise margin at the HIGH level for each connected device

VnH

0.2VDVDD

(including hysteresis)

(1)

In master mode, the maximum speed is 375 kHz.

(2)

Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges

of SCL. TI recommends that a 2-k

Ω pullup resistor be used to avoid potential timing issues.

(3)

A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.

This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the

standard-mode I2C bus specification) before the SCL line is released.

(4)

Cb = total capacitance of one bus line in pF

Electrical Specifications

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