TAS3202 datasheet(40/66 Pages) TI1

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XTALI

MCLKO

MCLKI

tw(MCLKI)

tf(MCLKO)

tc(1)

tc(2)

tc(3)

tw(MCLKO)

tr(MCLKO)

td(MI-MO)

T0088-01

TAS3202

SLES208B – JUNE 2009 – REVISED MARCH 2011

www.ti.com

8.6

Timing Characteristics

The following sections describe the timing characteristics of the TAS3202.

8.7

Master Clock

over recommended operating conditions (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

f(XTAL_IN)

Frequency, XTAL_IN (1/ tc(1))

See (1)

512Fs

tc(1)

Cycle time, XTAL_IN

1÷512Fs

Sec

f(MCLK_IN)

Frequency, MCLK_IN (1/ tc(2))

512Fs

tw(MCLK_IN)

Pulse duration, MCLK_IN high

See (2)

0.4 tc(2)

0.5 tc(2)

0.6 tc(2)

Crystal frequency deviation

ppm

f(MCLKO)

Frequency, MCLKO (1/ tc(3))

256Fs

tr(MCLKO)

Rise time, MCLKO

CL = 30 pF

tf(MCLKO)

Fall time, MCLKO

CL = 30 pF

tw(MCLK_IN)

Pulse duration, MCLKO high

See (3)

HMCLKO

XTAL_IN master clock

source

MCLKO jitter

MCLK_IN master clock

See (4)

source

MCLKO = MCLK_IN

See (5)

Delay time, MCLK_IN rising

td(MI-MO)

edge to MCLKO rising edge

MCLKO < MCLK_IN

See (5) (6)

(1)

Duty cycle is 50/50.

(2)

Period of MCLK_IN = TMCLK_IN = 1/fMCLK_IN

(3)

HMCLKO = 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLK_IN when MCLKO = MCLK_IN. When MCLKO = 0.5 MCLK_IN or

0.25 MCLK_IN, the duty cycle of MCLKO is typically 50%.

(4)

When MCLKO is derived from MCLK_IN, MCLKO jitter = MCLK_IN jitter

(5)

Only applies when MCLK_IN is selected as master source clock

(6)

Also applies to MCLKO falling edge when MCLKO = MCLK_IN/2 or MCLK_IN/4

Figure 8-3. Master Clock Signal Timing Waveforms

Electrical Specifications

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