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PXD20 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc |
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PXD20 Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 130 page  Pinout and signal descriptions PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor 32 DDR_DQ[11] DRAM Data Bus [11] I/O DDR PCR[257] None, None J1 DDR_DQ[10] DRAM Data Bus [10] I/O DDR PCR[258] None, None K4 DDR_DQ[9] DRAM Data Bus [9] I/O DDR PCR[259] None, None K1 DDR_DQ[8] DRAM Data Bus [8] I/O DDR PCR[260] None, None L1 DDR_DQ[7] DRAM Data Bus [7] I/O DDR PCR[261] None, None L4 DDR_DQ[6] DRAM Data Bus [6] I/O DDR PCR[262] None, None M4 DDR_DQ[5] DRAM Data Bus [5] I/O DDR PCR[263] None, None M1 DDR_DQ[4] DRAM Data Bus [4] I/O DDR PCR[264] None, None N4 DDR_DQ[3] DRAM Data Bus [3] I/O DDR PCR[265] None, None N1 DDR_DQ[2] DRAM Data Bus [2] I/O DDR PCR[266] None, None P4 DDR_DQ[1] DRAM Data Bus [1] I/O DDR PCR[267] None, None P1 DDR_DQ[0] DRAM Data Bus [0] I/O DDR PCR[268] None, None R1 DRAM Data Strobes DDR_DQS[3] DRAM Data Strobe [3] I/O DDR PCR[232] None, None B3 DDR_DQS[2] DRAM Data Strobe [2] I/O DDR PCR[231] None, None G2 DDR_DQS[1] DRAM Data Strobe [1] I/O DDR PCR[230] None, None K2 DDR_DQS[0] DRAM Data Strobe [0] I/O DDR PCR[229] None, None N2 DRAM Data Enables DDR_DM[3] DRAM Data Enable [3] Output DDR PCR[236] Output, None B4 DDR_DM[2] DRAM Data Enable [2] Output DDR PCR[235] Output, None G3 DDR_DM[1] DRAM Data Enable [1] Output DDR PCR[234] Output, None K3 DDR_DM[0] DRAM Data Enable [0] Output DDR PCR[233] Output, None P3 DRAM Address DDR_A[15] DRAM address [15] Output DDR PCR[217] Output, None B15 DDR_A[14] DRAM address [14] Output DDR PCR[216] Output, None D15 DDR_A[13] DRAM address [13] Output DDR PCR[215] Output, None D14 DDR_A[12] DRAM address [12] Output DDR PCR[214] Output, None A14 DDR_A[11] DRAM address [11] Output DDR PCR[213] Output, None D13 Table 6. DRAM interface pin summary (continued) Port pin1 Function I/O direction Pad type PCR RESET config2 Pin number 416 TEPBGA |
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