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MSP430F6779IPEUR Datasheet(PDF) 144 Page - Texas Instruments |
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MSP430F6779IPEUR Datasheet(HTML) 144 Page - Texas Instruments |
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144 / 157 page  PJ.1/MCLK/TDI/TCLK PJ.2/ADC10CLK/TMS PJ.3/ACLK/TCK 1 0 PJDIR.x PJIN.x EN 1 0 DV SS DV CC PJREN.x 1 PJDS.x 0: Low drive 1: High drive D DVSS To JTAG Pad Logic PJSEL.x 01 00 MCLK/ADC10CLK/ACLK PJOUT.x From JTAG 10 11 From JTAG Bus Holder PJ.0/SMCLK/TDO PJSEL.x 1 0 PJDIR.x PJIN.x EN SMCLK PJOUT.x 1 0 DV SS DV CC PJREN.x 1 PJDS.0 0: Low drive 1: High drive D DVCC Pad Logic From JTAG From JTAG 01 00 10 11 Bus Holder ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x MSP430F676x MSP430F674x SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013 www.ti.com Port J, J.0, JTAG pin TDO, Input/Output With Schmitt Trigger or Output Port J, J.1 to J.3, JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output 144 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated |
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