AD9142BCPZ datasheet(36/65 Pages) AD

36 / 65 page

AD9142

Data Sheet

Rev. 0 | Page 36 of 64

DAC INPUT CLOCK CONFIGURATIONS

The AD9142 DAC sample clock (DACCLK) can be sourced

directly or by clock multiplying. Clock multiplying employs the

on-chip phase-locked loop (PLL) that accepts a reference clock

operating at a submultiple of the desired DACCLK rate. The

PLL then multiplies the reference clock up to the desired DACCLK

frequency, which can then be used to generate all of the internal

clocks required by the DAC. The clock multiplier provides a

high quality clock that meets the performance requirements of

most applications. Using the on-chip clock multiplier removes

the burden of generating and distributing the high speed DACCLK.

The second mode bypasses the clock multiplier circuitry and lets

DACCLK be sourced directly to the DAC core. This mode lets the

user source a very high quality clock directly to the DAC core.

DRIVING THE DACCLK AND REFCLK INPUTS

The DACCLK and REFCLK differential inputs share similar

clock receiver input circuitry. Figure 51 shows a simplified circuit

diagram of the input. The on-chip clock receiver has a differential

input impedance of about 10 kΩ. It is self biased to a common-

mode voltage of about 1.25 V. The inputs can be driven by

differential PECL or LVDS drivers with ac coupling between the

clock source and the receiver.

Figure 51. Clock Receiver Input Simplified Equivalent Circuit

The minimum input drive level to the differential clock input is

100 mV p-p differential. The optimal performance is achieved

when the clock input signal is between 800 mV p-p differential

and 1.6 V p-p differential. Whether using the on-chip clock

multiplier or sourcing the DACCLK directly, the input clock

signal to the device must have low jitter and fast edge rates to

optimize the DAC noise performance.

DIRECT CLOCKING

Direct clocking with a low noise clock produces the lowest noise

spectral density at the DAC outputs. To select the differential

CLK inputs as the source for the DAC sampling clock, set the

PLL enable bit (Register 0x12[7]) to 0. This powers down the

internal PLL clock multiplier and selects the input from the

DACCLKP and DACCLKN pins as the source for the internal

DAC sampling clock. The REFCLK input can remain floating.

The device also has clock duty cycle correction circuitry and

differential input level correction circuitry. Enabling these circuits

can provide improved performance in some cases. The control

bits for these functions are in Register 0x10 and Register 0x11.

CLOCK MULTIPLICATION

The on-chip PLL clock multiplier circuit generates the DAC

sample rate clock from a lower frequency reference clock. When

the PLL enable bit (Register 0x12[7]) is set to 1, the clock

multiplication circuit generates the DAC sampling clock from

the lower rate REFCLK input and the DACCLK input is left

floating. The functional diagram of the clock multiplier is

shown in Figure 52.

The clock multiplication circuit operates such that the VCO

outputs a frequency, fVCO, equal to the REFCLK input signal

frequency multiplied by N1 × N0. N1 is the divide ratio of the

loop divider; N0 is the divide ratio of the VCO divider.

fVCO = fREFCLK × (N1 × N0)

The DAC sample clock frequency, fDACCLK, is equal to

fDACCLK = fREFCLK × N1

The output frequency of the VCO must be chosen to keep fVCO

in the optimal operating range of 1.0 GHz to 2.1 GHz. It is

important to select a frequency of the reference clock and values

of N1 and N0 so that the desired DACCLK frequency can be

synthesized and the VCO output frequency is in the correct range.

Figure 52. PLL Clock Multiplication Circuit

1.25V

5kΩ

100Ω

5kΩ

DACCLKP/

REFP/SYNCP

AD9142

DACCLKN/

REFN/SYNCN

1~100nF

RECOMMENDED

EXTERNAL

CIRCUITRY

PHASE

FREQUENCY

DETECTION

CHARGE

PUMP

PLL CHARGE

PUMP CURRENT

REG 0x14[4:0]

DIVIDE BY

2, 4, 8, OR 16

LOOP DIVIDER

REG 0x15[1:0]

DIVIDE BY

1, 2, OR 4

VCO DIVIDER

REG 0x15[3:2]

ON-CHIP

LOOP FILTER

PLL LOOP BW

REG 0x14[7:5]

VCO

(1GHz~2.1GHz)

ADC

VCO CONTROL

VOLTAGE

REG 0x16[3:0]

REFP/SYNCP

(PIN 2)

REFN/SYNCN

(PIN 3)

DACCLKN

(PIN 62)

DACCLKP

(PIN 61)

DACCLK

PLL ENABLE

REG 0x12[7]

AD9142BCPZ Datasheet(PDF) 36 Page - Analog Devices

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