AD9142BCPZ datasheet(20/65 Pages) AD

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AD9142

Data Sheet

Rev. 0 | Page 20 of 64

DATA INTERFACE

LVDS INPUT DATA PORTS

The AD9142 has a 16-bit LVDS bus that accepts 16-bit I and Q

data either in word wide (16-bit) or byte wide (8-bit) formats. In

the word wide interface mode, the data is sent over the entire

16-bit data bus. In the byte wide interface mode, the data is sent

over the lower 8-bit (D7 to D0) LVDS bus. Table 11 lists the pin

assignment of the bus and the SPI register configuration for

each mode.

Table 11. LVDS Data Input Modes

Interface Mode

Pin Assignment

SPI Register Configuration

Word

D15 to D0

Byte

D7 to D0

WORD INTERFACE MODE

In word mode, the digital clock input (DCI) signal is a reference

bit that generates a double data rate (DDR) data sampling clock.

Time align the DCI signal with the data. The IDAC data follows

the rising edge of the DCI, and the QDAC data follows the

falling edge of the DCI, as shown in Figure 33.

Figure 33. Timing Diagram for Word Mode

BYTE INTERFACE MODE

In byte mode, the required sequence of the input data stream is

I[15:8], I[7:0], Q[15:8], Q[7:0]. A frame signal is required to

align the order of input data bytes properly. Time align both the

DCI signal and frame signal with the data. The rising edge of

the frame indicates the start of the sequence. The frame can be

either a one shot or periodical signal as long as its first rising

edge is correctly captured by the device. For a one shot frame,

the frame pulse needs to hold at high for at least one DCI cycle.

For a periodical frame, the frequency needs to be

fDCI/(2 × n)

where n is a positive integer, that is, 1, 2, 3, …

Figure 34 is an example of signal timing in byte mode.

Figure 34. Timing Diagram for Byte Mode

DATA INTERFACE CONFIGURATION OPTIONS

To provide more flexibility for the data interface, some

additional options are listed in Table 12.

Table 12. Data Interface Configuration Options

Function

Data Format (Bit 7)

Select between binary and twos

complement formats.

Data Pairing (Bit 6)

Indicate I/Q data pairing on data input.

This allows the I and Q data that is

received to be paired in various ways.

Data Bus Invert (Bit 5)

Swaps the bit order of the data input

port. Remaps the input data from

D[15:0] to D[0:15].

WORD MODE

DCI

INPUT DATA[15:0]

I0[15:8]

I0[7:0]

Q0[15:8]

Q0[7:0]

BYTE MODE

DCI

FRAME

INPUT DATA[7:0]

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