AD9142BCPZ datasheet(29/65 Pages) AD

29 / 65 page

Data Sheet

AD9142

Rev. 0 | Page 29 of 64

SPI Initiated Update

In the SPI initiated update method, the user simply toggles

the NCO settings. The NCO is updated on the rising edge (from

0 to 1) in this bit. Register 0x30[1] (NCO_SPI_UPDATE_ACK)

goes high when the NCO is updated. A falling edge (from 1 to

0) in Register 0x30[0] clears Bit 1 of Register 0x30 and prepares

the NCO for the next update operation. This update method is

recommended when there is no requirement to align the DAC

output from multiple devices because SPI writes to multiple

devices are asynchronous.

Frame Initiated Update

When the DAC output from multiple devices needs to be well

aligned with NCO turned on, the frame initiated update is

recommended. In this method, the NCOs from multiple devices

are updated at the same time upon the rising edge of the frame

signal. To use this update method, the FRAME_RESET_MODE

(Register 0x22[1:0]) needs to be set in NCO only or FIFO and

NCO, depending on whether FIFO reset is needed at the same

time. The second step is to ensure that the reset mode is in one

shot mode (EN_CON_FRAME_RESET, Register 0x22[2] = 0).

When this second step is completed, the NCO waits for a valid

frame pulse and updates the FTW accordingly. The user can verify

if the frame pulse is correctly received by reading Register 0x30[6]

(NCO_FRAME_ UPDATE_ACK) wherein a 1 indicates a

complete update operation. See the FIFO Operation section for

information to generate a valid frame pulse.

DATAPATH CONFIGURATION

Configuring the AD9142 datapath starts with the following four

parameters:

•

The application requirements of the input data rate

•

The interpolation ratio

•

The output signal center frequency

•

The output signal bandwidth

Given these four parameters, the first step in configuring the

datapath is to verify that the device supports the desired input

data rate, the DAC sampling rate, and the bandwidth requirements.

After this verification, the modes of the interpolation filters can be

chosen. If the output signal center frequency is different from the

baseband input center frequency, additional frequency offset

requirements are determined and applied with on-chip digital

modulation.

DIGITAL QUADRATURE GAIN AND PHASE

ADJUSTMENT

The digital quadrature gain and phase adjustment function

enables compensation of the gain and phase imbalance of the I

and Q paths caused by analog mismatches between DAC I/Q

outputs, quadrature modulator I/Q baseband inputs, and

DAC/modulator interface I/Q paths. The undesired imbalances

cause unwanted sideband signal to appear at the quadrature

modulator output with significant energy. Tuning the

quadrature gain and phase adjust values optimizes image

rejection in single sideband radios.

Quadrature Gain Adjustment

Ordinarily, the I and Q channels have the same gain or signal

magnitude. The quadrature gain adjustment is used to balance the

gain between the I and Q channels. The digital gain of the I and Q

channels can be adjusted independently through two 6-bit registers,

IDAC_GAIN_ADJ (Register 0x3F[5:0]) and QDAC_GAIN_ADJ

(Register 0x40[5:0]). The range of the adjustment is [0, 2] or [−∞,

6 dB] with a step size of 2−5 (−30 dB). The default setting is 0x20,

corresponding to a gain equal to 1 or 0 dB.

Quadrature Phase Adjustment

Under normal circumstances, I and Q channels have an angle of

precisely 90 degrees between them. The quadrature phase adjust-

ment is used to change the angle between the I and Q channels.

IQ_PHASE_ADJ[12:0] (Register 0x37 and Register 0x38) provide

an adjustment range of ±14 degrees with a resolution of 0.0035

degrees. If the original angle is precisely 90 degrees, setting

IQ_PHASE_ADJ[12:0] to 0x0FFF adds approximately 14 degrees

between I and QDAC outputs, creating an angle of 104 degrees

between the channels. Likewise, if the original angle is precisely

90 degrees, setting IQ_PHASE_ADJ[12:0] to 0x1000 adds

approximately −14 degrees between the I and QDAC outputs,

creating an angle of 76 degrees between the channels.

DC OFFSET ADJUSTMENT

The dc value of the I datapath and the Q datapath can be controlled

independently by adjusting the values in the two 16-bit registers,

IDAC_DC_OFFSET, Bits[15:0] and QDAC_DC_OFFSET,

Bits[15:0] (Register 0x3B through Register 0x3E). These values

are added directly to the datapath values. Care should be taken

not to overrange the transmitted values.

As shown in Figure 46, the DAC offset current varies as a function

of the I/QDAC_DC_OFFSET values. Figure 46 shows the

nominal current of the positive node of the DAC output, IOUTP,

when the digital inputs are fixed at midscale (0x0000, twos

complement data format) and the DAC offset value is swept from

0x0000 to 0xFFFF. Because IOUTP and IOUTN are complementary

current outputs, the sum of IOUTP and IOUTN is always 20 mA.

Figure 46. DAC Output Currents vs. DAC Offset Value

0x0000

0x4000

0x8000

0xC000

0xFFFF

DAC OFFSET VALUE

AD9142BCPZ Datasheet(PDF) 29 Page - Analog Devices

AD9142BCPZ Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL