AD9142BCPZ datasheet(23/65 Pages) AD

23 / 65 page

Data Sheet

AD9142

Rev. 0 | Page 23 of 64

FIFO OPERATION

As is shown in the Data Interface section, the AD9142 adopts

source synchronous clocking in the data receiver. The nature of

source synchronous clocking is the creation of a separate clock

domain at the receiving device. In the DAC, it is the DAC clock

domain, that is, the DACCLK. Therefore, there are two clock

domains inside of the DAC: the DCI and the DACCLK. Often,

these two clock domains are not synchronous, requiring an

additional stage to adjust the timing for proper data transfer. In

the AD9142, a FIFO stage is inserted between the DCI and

DACCLK domains to transfer the received data into the core

clock domain (DACCLK) of the DAC.

The AD9142 contains a 2-channel, 16-bit wide, 8-word deep

FIFO. The FIFO acts as a buffer that absorbs timing variations

between the two clock domains. The timing budget between the

two clock domains in the system is significantly relaxed due to

the depth of the FIFO.

Figure 37 shows the block diagram of the datapath through the

FIFO. The input data is latched into the device, formatted, and

then written into the FIFO register, which is determined by the

FIFO write pointer. The value of the write pointer is incremented

every time a new word is loaded into the FIFO. Meanwhile, data

is read from the FIFO register, which is determined by the read

pointer, and fed into the digital datapath. The value of the read

pointer is incremented every time data is read into the datapath

from the FIFO. The FIFO pointers are incremented at the data

rate, which is the DACCLK rate divided by the interpolation rate.

Valid data is transmitted through the FIFO as long as the FIFO

does not overflow (full) or underflow (empty). An overflow or

underflow condition occurs when the write pointer and read

pointer point to the same FIFO slot. This simultaneous access of

data leads to unreliable data transfer through the FIFO and must be

avoided.

Normally, data is written to and read from the FIFO at the same

rate to maintain a constant FIFO depth. If data is written to the

FIFO faster than data is read, the FIFO depth increases. If data

is read from the FIFO faster than data is written to it, the FIFO

depth decreases. For optimal timing margin, maintain the FIFO

depth near half full (a difference of four between the write

pointer and read pointer values). The FIFO depth represents the

FIFO pipeline delay and is part of the overall latency of the

AD9142.

Figure 37. Block Diagram of FIFO

DATA

RECEIVER

I DATA PATH

Q DATA PATH

I DAC

DCI

INPUT DATA [15:0]

FRAME

RETIMED DCI

SPI FIFO RESET

REG 0x25[0]

÷INT

DACCLK

FIFO LEVEL REQUEST

REG 0x23

Q DAC

FIFO WRITE CLOCK

FIFO READ CLOCK

WRITE

POINTER

READ

POINTER

FIFO SLOT 0

FIFO SLOT 1

FIFO SLOT 2

FIFO SLOT 3

FIFO SLOT 4

FIFO SLOT 5

FIFO SLOT 6

FIFO SLOT 7

FIFO LEVEL

RESET

LOGIC

FIFO

DATA

FORMAT

I[15:0]

Q[15:0]

I/Q[31:0]

LATCHED

DATA [15:0]

AD9142BCPZ Datasheet(PDF) 23 Page - Analog Devices

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