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AD9142BCPZ Datasheet(PDF) 44 Page - Analog Devices |
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AD9142BCPZ Datasheet(HTML) 44 Page - Analog Devices |
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44 / 65 page  AD9142 Data Sheet Rev. 0 | Page 44 of 64 SPI CONFIGURE REGISTER Address: 0x00, Reset: 0x00, Name: Common Table 23. Bit Descriptions for Common Bits Bit Name Settings Description Reset Access 6 SPI_LSB_FIRST Serial port communication, MSB-first or LSB-first selection. 0x0 RW 0 MSB first. 1 LSB first. 5 DEVICE_RESET The device resets when 1 is written to this bit. DEVICE_RESET is a self clear bit. After the reset, the bit returns to 0 automatically. The readback is always 0. 0x0 RW POWER-DOWN CONTROL REGISTER Address: 0x01, Reset: 0xC0, Name: PD_CONTROL Table 24. Bit Descriptions for PD_CONTROL Bits Bit Name Settings Description Reset Access 7 PD_IDAC The IDAC is powered down when PD_IDAC is set to 1. This bit powers down only the analog portion of the IDAC. The IDAC digital data path is not affected. 0x1 RW 6 PD_QDAC The QDAC is powered down when PD_QDAC is set to 1. This bit powers down only the analog portion of the QDAC. The QDAC digital data path is not affected. 0x1 RW 5 PD_DATARCV The data interface circuitry is powered down when PD_DATARCV is set to 1. This bit powers down the data interface and the write side of the FIFO. 0x0 RW 2 PD_DEVICE The bandgap circuitry is powered down when set to 1. This bit powers down the entire chip. 0x0 RW 1 PD_DACCLK The DAC clocking powers down when PD_DEVICE is set to 1. This bit powers down the DAC clocking path and, thus, the majority of the digital functions. 0x0 RW 0 PD_FRAME The frame receiver powers down when PD_FRAME is set to 1. The frame signal is internally pulled low. Set to 1 when frame is not used. 0x0 RW INTERRUPT ENABLE0 REGISTER Address: 0x03, Reset: 0x00, Name: INTERRUPT_ENABLE0 Table 25. Bit Descriptions for INTERRUPT_ENABLE0 Bits Bit Name Settings Description Reset Access 6 ENABLE_SYNC_LOST Enable interrupt for sync lost. 0x0 RW 5 ENABLE_SYNC_LOCKED Enable interrupt for sync lock. 0x0 RW 4 ENABLE_SYNC_DONE Enable interrupt for sync done. 0x0 RW 3 ENABLE_PLL_LOST Enable interrupt for PLL lost. 0x0 RW 2 ENABLE_PLL_LOCKED Enable interrupt for PLL locked. 0x0 RW 1 ENABLE_OVER_THRESHOLD Enable interrupt for overthreshold. 0x0 RW 0 ENABLE_DACOUT_MUTED Enable interrupt for DACOUT muted. 0x0 RW INTERRUPT ENABLE1 REGISTER Address: 0x04, Reset: 0x00, Name: INTERRUPT_ENABLE1 Table 26. Bit Descriptions for INTERRUPT_ENABLE1 Bits Bit Name Settings Description Reset Access 2 ENABLE_FIFO_UNDERFLOW Enable interrupt for FIFO underflow. 0x0 RW 1 ENABLE_FIFO_OVERFLOW Enable interrupt for FIFO overflow. 0x0 RW 0 ENABLE_FIFO_WARNING Enable interrupt for FIFO warning. 0x0 RW |
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