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AD9142BCPZ Datasheet(PDF) 59 Page - Analog Devices |
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AD9142BCPZ Datasheet(HTML) 59 Page - Analog Devices |
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59 / 65 page  Data Sheet AD9142 Rev. 0 | Page 59 of 64 DAC LATENCY AND SYSTEM SKEWS Figure 60. Breakdown of Pipeline Latencies DAC LATENCY VARIATIONS DACs, like any other devices with internal multiphase clocks, have an inherent pipeline latency variation. Figure 60 shows the breakdown of pipeline latencies in the AD9142. The highlighted section, including the FIFO and the clock generation circuitry, is where the pipeline latencies vary. Upon each power-on, the status of both the FIFO and the clock generation state machine is arbitrary. This leads to varying latency in these two blocks. FIFO LATENCY VARIATION There are eight data slots in the FIFO. The FIFO read and write pointers circulate the FIFO from Slot 0 to Slot 7 and back to Slot 0. The FIFO depth is defined as the number of FIFO slots that are required for the read pointer to catch the write pointer. It is also the time a particular piece of data stays in the FIFO from the point that it is written into the FIFO to the point where it is read out from the FIFO. Therefore, the latency of the FIFO is equivalent to its depth. Figure 61 is an example of FIFO latency variation. The latency in Case 2 is two data cycles longer than that in Case 1. If other latencies are the same, the skew between the DAC outputs in these two cases is, likewise, two data cycles. Therefore, to keep a constant FIFO latency, the FIFO depth needs to be reset to a pre- defined value. Theoretically, any value other than 0 is valid but typically it is set to 4 to maximize the capacity of absorbing the rate fluctuation between the read and write side. Figure 61. Example of FIFO Latency Difference Figure 62 shows two equivalent cases of FIFO latency of four data cycles. Although neither the read nor the write pointer match each other in these two cases, the FIFO depth is the same in both cases. Also, note that the beginning slots of the data stream in the two cases are not the same, but the read and write pointers point to the same piece of data in both cases. This does not affect the alignment accuracy of the DAC outputs as long as the data and the DCIs are well aligned at multiple devices. Figure 62. Example of Equal FIFO Latencies FIFO DACCLK I AND Q DAC HB1 FIXED LATENCY HB2 HB3 OTHER DIGITAL FUNCTIONALITIES DACCLK/2 DACCLK/4 DACCLK/8 DCI FIFO WrPtr FIFO RdPtr VARYING LATENCY VARYING LATENCY FIXED LATENCY DIV 2 DIV 2 DIV 2 DATA INTERFACE DATA 2 DATA 3 DATA 4 DATA 5 FIFO CASE 1: LATENCY = 4 DCI CYCLES FIFO WrPtr FIFO RdPtr DATA 6 DATA 7 DATA 1 DATA 0 DATA 2 DATA 3 DATA 4 DATA 5 FIFO CASE 2: LATENCY = 6 DCI CYCLES FIFO WrPtr FIFO RdPtr DATA 6 DATA 7 DATA 1 DATA 0 DATA 2 DATA 3 DATA 4 DATA 5 FIFO LATENCY = 4 DCI CYCLES FIFO WrPtr FIFO RdPtr DATA 6 DATA 7 DATA 1 DATA 0 DATA 7 DATA 0 DATA 1 DATA 2 FIFO FIFO WrPtr FIFO RdPtr DATA 3 DATA 4 DATA 6 DATA 5 |
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