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AD9142BCPZ Datasheet(PDF) 55 Page - Analog Devices |
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AD9142BCPZ Datasheet(HTML) 55 Page - Analog Devices |
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55 / 65 page ![]() Data Sheet AD9142 Rev. 0 | Page 55 of 64 NCO_PHASE_OFFSET1 REGISTER Address: 0x36, Reset: 0x00, Name: NCO_PHASE_OFFSET1 Table 66. Bit Descriptions for NCO_PHASE_OFFSET1 Bits Bit Name Settings Description Reset Access [7:0] NCO_PHASE_OFFSET_MSB This register sets the initial phase of the complex carrier signal upon reset. The phase offset spans from 0 degrees to 360 degrees. Each bit represents an offset of 0.0055 degrees. This value is in twos complement format. 0x00 RW IQ_PHASE_ADJ0 REGISTER Address: 0x37, Reset: 0x00, Name: IQ_PHASE_ADJ0 Table 67. Bit Descriptions for IQ_PHASE_ADJ0 Bits Bit Name Settings Description Reset Access [7:0] IQ_PHASE_ADJ_LSB See Register 0x38. 0x00 RW IQ_PHASE_ADJ1 REGISTER Address: 0x38, Reset: 0x000, Name: IQ_PHASE_ADJ1 Table 68. Bit Descriptions for IQ_PHASE_ADJ1 Bits Bit Name Settings Description Reset Access [4:0] IQ_PHASE_ADJ_MSB IQ phase adjust, Bits[12:0], is used to insert a phase offset between the I and Q datapaths. It provides an adjustment range of ±14 degrees with a step of 0.0035 degrees. This value is in twos complement. See the Quadrature Phase Adjustment section for more information. 0x0 RW IDAC_DC_OFFSET0 REGISTER Address: 0x3B, Reset: 0x00, Name: IDAC_DC_OFFSET0 Table 69. Bit Descriptions for IDAC_DC_OFFSET0 Bits Bit Name Settings Description Reset Access [7:0] IDAC_DC_OFFSET_LSB See Register 0x3C. 0x00 RW IDAC_DC_OFFSET1 REGISTER Address: 0x3C, Reset: 0x00, Name: IDAC_DC_OFFSET1 Table 70. Bit Descriptions for IDAC_DC_OFFSET1 Bits Bit Name Settings Description Reset Access [7:0] IDAC_DC_OFFSET_MSB IDAC DC offset, Bits[15:0], is a dc value that is added directly to the sample values written to the IDAC. 0x00 RW QDAC_DC_OFFSET0 REGISTER Address: 0x3D, Reset: 0x00, Name: QDAC_DC_OFFSET0 Table 71. Bit Descriptions for QDAC_DC_OFFSET0 Bits Bit Name Settings Description Reset Access [7:0] QDAC_DC_OFFSET_LSB See Register 0x3E. 0x00 RW |
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