PIC14000 datasheet(41/153 Pages) MICROCHIP

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Preliminary

DS40122B-page 41

PIC14000

7.0

INTER-INTEGRATED CIRCUIT

SERIAL PORT (I2C

™)

The I2C module is a serial interface useful for

communicating with other peripheral or microcontroller

devices. These peripheral devices may be serial

EEPROMs,

shift

registers,

display

drivers,

A/D

converters, etc. The I2C module is compatible with the

following interface speciﬁcations:

• Inter-Integrated Circuit (I2C)

• System Management Bus (SMBus)

This section provides an overview of the Inter-IC(I2C)

bus. The I2C bus is a two-wire serial interface

developed by the Philips Corporation. The original

speciﬁcation, or standard mode, was for data transfers

of up to 100 Kbps. An enhanced speciﬁcation, or fast

mode, supports data transmission up to 400 Kbps.

Both standard mode and fast mode devices will

inter-operate if attached to the same bus.

The I2C interface employs a comprehensive protocol to

ensure reliable transmission and reception of data.

When transmitting data, one device is the “master”

(generates the clock) while the other device(s) acts as

the “slave”. All portions of the slave protocol are

implemented in the I2C module’s hardware, except

general call support, while portions of the master proto-

col will need to be addressed in the PIC14000 soft-

ware.

Table 7-1

deﬁnes

some

the

I2C

bus

terminology. For additional information on the I2C inter-

face speciﬁcation, please refer to the Philips Corpora-

tion document

“The I 2C-bus and How to Use It”.

Note:

The I2C module on PIC14000 only

supports I2C mode. This is different from

the

standard

module

used

the

PIC16C7X family, which supports both

I2C and SPI modes. Caution should be

exercised to avoid enabling SPI mode on

the PIC14000.

In the I2C interface protocol each device has an

address. When a master wishes to initiate a data

transfer, it ﬁrst transmits the address of the device that

it wishes to talk to. All devices “listen” to see if this is

their address. Within this address, a bit speciﬁes if the

master wishes to read from or write to the slave device.

The master and slave are always in opposite modes

(transmitter/receiver) of operation during a data

transfer. They may operate in either of these two

states:

• Master-transmitter and Slave-receiver

• Slave-transmitter and Master-receiver

In both cases the master generates the clock signal.

The output stages of the clock (SCL) and data (SDA)

lines must have an open-drain or open-collector in

order to perform the wired-AND function of the bus.

External pull-up resistors are used to ensure a high

level when no device is pulling the line down. The

number of devices that may be attached to the I2C bus

is limited only by the maximum bus loading speciﬁca-

tion of 400 pF.

7.1

Initiating and Terminating Data

Transfer

During times of no data transfer (idle time), both the

clock line (SCL) and the data line (SDA) are pulled high

through the external pull-up resistors. The START and

STOP

determine

the

start

and

stop

data

transmission. The START is deﬁned as a high to low

transition of SDA when SCL is high. The STOP is

deﬁned as a low to high transition of SDA when SCL is

high. Figure 7-1 shows the START and STOP. The

master generates these conditions for starting and ter-

minating data transfer. Due to the deﬁnition of the

START and STOP, when data is being transmitted the

SDA line can only change state when the SCL line is

low.

FIGURE 7-1:

I2C START AND STOP CONDITIONS

Start

Condition

Change

of Data

Allowed

Change

of Data

Allowed

Stop

Condition

SDA

SCL

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