PIC14000 datasheet(82/153 Pages) MICROCHIP

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PIC14000

DS40122B-page 82

Preliminary

10.6

Interrupts

The PIC14000 has several sources of interrupt:

• External interrupt from OSC1/PBTN pin

•I2C port interrupt

• PORTC interrupt on change (pins RC<7:4> only)

• Timer0 overﬂow

• A/D timer overﬂow

• A/D converter capture event

• Programmable reference comparator interrupt

This section addresses the external and Timer0

interrupts only. Refer to the appropriate sections for

description of the serial port, programmable reference

and A/D interrupts.

INTCON records individual interrupt requests in ﬂag

bits. It also has individual and global enable bits. The

peripheral interrupt ﬂags reside in the PIR1 register.

Peripheral interrupt enable interrupts are contained in

the PIE1 register.

Global

interrupt

masking

controlled

GIE

(INTCON<7>). Individual interrupts can be disabled

through their corresponding mask bit in the INTCON

When an interrupt is serviced, the GIE is cleared to

disable any further interrupt, the return address is

pushed onto the stack and the PC is loaded with

0004h, the interrupt vector. For external interrupt

events, such as the I2C interrupt, the interrupt latency

will be 3 or 4 instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for 1 or 2 cycle instructions. Once in the

interrupt service routine the source(s) of the interrupt

can be determined by polling the interrupt ﬂag bits. The

interrupt ﬂag bit(s) must be cleared in software before

re-enabling

interrupts

avoid

inﬁnite

interrupt

requests.

Individual

interrupt

ﬂag

bits

are

set

regardless of the status of their corresponding mask bit

or the GIE bit to allow polling.

The return from interrupt instruction, RETFIE, exits the

interrupt routine as well as sets the GIE bit to re-enable

interrupts.

Note 1: The individual interrupt ﬂags will be set by

the speciﬁed condition even though the

corresponding

interrupt

enable

bit

cleared (interrupt disabled) or the GIE bit is

cleared (all interrupts disabled).

Note 2: If an interrupt occurs while the Global

Interrupt Enable (GIE) bit is being cleared,

the

GIE

bit

may

unintentionally

re-enabled by the user’s Interrupt Service

Routine (the RETFIE instruction). The

events that would cause this to occur are:

An instruction clears the GIE bit while an

interrupt is acknowledged.

The program branches to the interrupt vector

and executes the Interrupt Service Routine.

The interrupt service routine completes with the

execution of the RETFIE instruction. This causes

the GIE bit to be set (enables interrupts), and the

program returns to the instruction after the one

which was meant to disable interrupts.

The method to ensure that interrupts are globally

disabled is:

Ensure that the GIE bit was cleared by the

instruction, as shown in the following code:

LOOP: BCF

INTCON,GIE

; Disable Global Interrupts

BTFSC INTCON,GIE

; Global Interrupts Disabled?

GOTO

LOOP

; No, try again

; Yes, continue with program

;

flow

FIGURE 10-9: INTERRUPT LOGIC SCHEMATIC

PBIF

PBIE

ADCIF

ADCIE

I2CIF

I2CIE

OVFIF

OVFIE

CMIF

CMIE

T0IF

T0IE

PEIE

Wake-up (If in SLEEP mode)

or terminate long write

Interrupt to CPU

PEIF

RCIF

RCIE

GIE

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