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EP2C8A Datasheet(PDF) 136 Page - Altera Corporation |
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EP2C8A Datasheet(HTML) 136 Page - Altera Corporation |
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136 / 168 page  5–46 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2008 Timing Specifications Maximum Input and Output Clock Rate Maximum clock toggle rate is defined as the maximum frequency achievable for a clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated clock I/O pin. The maximum clock toggle rate is different from the maximum data bit rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same I/O pin. Table 5–44 specifies the maximum input clock toggle rates. Table 5–45 specifies the maximum output clock toggle rates at default load. Table 5–46 specifies the derating factors for the output clock toggle rate for non-default load. To calculate the output toggle rate for a non-default load, use this formula: The toggle rate for a non-default load LVDS — tOP 1216 1275 2089 2184 2272 2278 ps tDI P 1340 1407 2297 2421 2545 2545 ps RSDS — tOP 1216 1275 2089 2184 2272 2278 ps tDIP 1340 1407 2297 2421 2545 2545 ps MINI_LVDS — tOP 1216 1275 2089 2184 2272 2278 ps tDIP 1340 1407 2297 2421 2545 2545 ps PCI — tOP 989 1036 2070 2214 2352 2358 ps tDIP 1113 1168 2278 2451 2625 2625 ps PCI-X — tOP 989 1036 2070 2214 2352 2358 ps tDIP 1113 1168 2278 2451 2625 2625 ps Notes to Table 5–43: (1) This is the default setting in the Quartus II software. (2) These numbers are for commercial devices. (3) These numbers are for automotive devices. Table 5–43. Cyclone II I/O Output Delay for Row Pins (Part 4 of 4) I/O Standard Drive Strength Parameter Fast Corner –6 Speed Grade –7 Speed Grade (2) –7 Speed Grade (3) –8 Speed Grade Unit Industrial /Auto- motive Commer- cial |
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