ADSP-TS101S datasheet(30/48 Pages) AD

30 / 48 page

Rev. C

Page 30 of 48

May 2009

ADSP-TS101S

Table 30. Link Ports—Receive

Parameter

Min

Max

Unit

Timing Requirements

tLXCLK_RX

1, 2

Receive Link Clock Period

0.9  LR  tCCLK

1.1  LR  tCCLK

tLXCLKH_RX

Receive Link Clock Width High

0.33  tLXCLK_RX

0.66  tLXCLK_RX

tLXCLKH_RX

Receive Link Clock Width High

0.4  tLXCLK_RX

0.6  tLXCLK_RX

tLXCLKL_RX

Receive Link Clock Width Low

0.33  tLXCLK_RX

0.66  tLXCLK_RX

tLXCLKL_RX

Receive Link Clock Width Low

0.4  tLXCLK_RX

0.6  tLXCLK_RX

tDIS

LxDAT7–0 Input Setup

0.6

tDIH

LxDAT7–0 Input Hold

0.6

Switching Characteristics

tCONNV

Connectivity Pulse Valid

2.5  tLXCLK_RX

tCONNOW

Connectivity Pulse Output Width

1.5  tLXCLK_RX

1 The link clock ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.

2 The maximum LxCLK is 125 MHz. LR = 2 may not be used when CCLK  250 MHz.

3 The formula for this parameter applies when LR is 2.

4 The formula for this parameter applies when LR is 3, 4, or 8.

Figure 18. Link Ports—Receive

LxCLKIN

LxCLKOUT

LxDAT7–0

LxDIR

tLxCLK_Rx

tCONNV

tLxCLKH_Rx

tLxCLKL_Rx

tCONNOW

tDIS

tDIH

tDIS

tDIH

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