ADSP-TS101S datasheet(29/48 Pages) AD

29 / 48 page

ADSP-TS101S

Rev. C

Page 29 of 48

May 2009

Link Ports Data Transfer and Token Switch Timing

Table 31, Table 32, Table 33, and Table 34 with Figure 17,

Figure 18, Figure 19, and Figure 20 provide the timing specifica-

tions for the link ports data transfer and token switch.

Table 29. Link Ports—Transmit

Parameter

Min

Max

Unit

Timing Requirements

tCONNS

Connectivity Pulse Setup

2  tCCLK + 3.5

tCONNS

Connectivity Pulse Setup

tCONNIW

Connectivity Pulse Input Width

tLXCLK_TX + 1

tACKS

Acknowledge Setup

0.5  tLXCLK_TX

Switching Characteristics

tLXCLK_TX

Transmit Link Clock Period

0.9  LR  tCCLK

1.1  LR  tCCLK

tLXCLKH_TX

Transmit Link Clock Width High

0.33  tLXCLK_TX

0.66  tLXCLK_TX

tLXCLKH_TX

Transmit Link Clock Width High

0.4  tLXCLK_TX

0.6  tLXCLK_TX

tLXCLKL_TX

Transmit Link Clock Width Low

0.33  tLXCLK_TX

0.66  tLXCLK_TX

tLXCLKL_TX

Transmit Link Clock Width Low

0.4  tLXCLK_TX

0.6  tLXCLK_TX

tDIRS

LxDIR Transmit Setup

0.5  tLXCLK_TX

2  tLXCLK_TX

tDIRH

LxDIR Transmit Hold

0.5  tLXCLK_TX

2  tLXCLK_TX

tDOS

LxDAT7–0 Output Setup

0.25  tLXCLK_TX – 1

tDOH

LxDAT7–0 Output Hold

0.25  tLXCLK_TX – 1

tDOS

LxDAT7–0 Output Setup

Greater of 0.8 or 0.17  tLXCLK_TX – 1

tDOH

LxDAT7–0 Output Hold

Greater of 0.8 or 0.17  tLXCLK_TX – 1

tLDOE

LxDAT7–0 Output Enable

tLDOD

LxDAT7–0 Output Disable

1 The formula for this parameter applies when LR is 2.

2 The formula for this parameter applies when LR is 3, 4, or 8.

3 LxCLKIN shows the connectivity pulse with each of the three possible transitions to “Acknowledge.” After a connectivity pulse low minimum, LxCLKIN may [1] return high

and remain high for “Acknowledge,” [2] return high and subsequently go low (meeting t

ACKS) for “Not Acknowledge,” or [3] remain low for “Not Acknowledge.”

4 The Link clock Ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register. The maximum LxCLK is 125 MHz. LR = 2 may not be used when CCLK  250 MHz.

5 This specification applies to the last data byte or the “Dummy” byte that follows the verification byte if enabled. For more information, see the ADSP-TS101 TigerSHARC

Processor Hardware Reference.

Figure 17. Link Ports—Transmit

LxCLKOUT

LxCLKIN

LxDIR

LxDAT7–0

tLxCLKL_Tx

tLxCLKH_Tx

tDIRS

tLxCLK_Tx

tCONNS

tDOS

tDOH

tDOS

tACKS

tDOH

tCONNIW

tDIRH

tLDOD

tLDOE

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