ADSP-TS101S datasheet(5/48 Pages) AD

5 / 48 page

ADSP-TS101S

Rev. C

Page 5 of 48

May 2009

The IALUs have hardware support for circular buffers, bit

reverse, and zero-overhead looping. Circular buffers facilitate

efficient programming of delay lines and other data structures

required in digital signal processing, and they are commonly

used in digital filters and Fourier transforms. Each IALU pro-

vides registers for four circular buffers, so applications can set

up a total of eight circular buffers. The IALUs handle address

pointer wraparound automatically, reducing overhead, increas-

ing performance, and simplifying implementation. Circular

buffers can start and end at any memory location.

Because the IALU’s computational pipeline is one cycle deep, in

most cases, integer results are available in the next cycle. Hard-

ware (register dependency check) causes a stall if a result is

unavailable in a given cycle.

PROGRAM SEQUENCER

The ADSP-TS101S processor’s program sequencer supports:

• A fully interruptible programming model with flexible pro-

gramming in assembly and C/C++ languages; handles

hardware interrupts with high throughput and no aborted

instruction cycles.

• An eight-cycle instruction pipeline—three-cycle fetch pipe

and five-cycle execution pipe—with computation results

available two cycles after operands are available.

• The supply of instruction fetch memory addresses; the

sequencer’s instruction alignment buffer (IAB) caches up

to five fetched instruction lines waiting to execute; the pro-

gram sequencer extracts an instruction line from the IAB

and distributes it to the appropriate core component for

execution.

• The management of program structures and determination

of program flow according to JUMP, CALL, RTI, RTS

instructions, loop structures, conditions, interrupts, and

software exceptions.

• Branch prediction and a 128-entry branch target buffer

(BTB) to reduce branch delays for efficient execution of

conditional and unconditional branch instructions and

zero-overhead looping; correctly predicted branches that

are taken occur with zero-to-two overhead cycles, over-

coming the three-to-six stage branch penalty.

• Compact code without the requirement to align code in

memory; the IAB handles alignment.

Interrupt Controller

The DSP supports nested and non-nested interrupts. Each

interrupt type has a register in the interrupt vector table. Also,

each has a bit in both the interrupt latch register and the inter-

rupt mask register. All interrupts are fixed as either level

sensitive or edge sensitive, except the IRQ3–0 hardware inter-

rupts, which are programmable.

The DSP distinguishes between hardware interrupts and soft-

ware exceptions, handling them differently. When a software

exception occurs, the DSP aborts all other instructions in the

instruction pipe. When a hardware interrupt occurs, the DSP

continues to execute instructions already in the instruction pipe.

Flexible Instruction Set

The 128-bit instruction line, which can contain up to four 32-bit

instructions, accommodates a variety of parallel operations for

concise programming. For example, one instruction line can

direct the DSP to conditionally execute a multiply, an add, and a

subtract in both computation blocks while it also branches to

another location in the program. Some key features of the

instruction set include:

• Enhanced instructions for communications infrastructure

to govern trellis decoding (for example, Viterbi and turbo

decoders) and despreading via complex correlations

• Algebraic assembly language syntax

• Direct support for all DSP, imaging, and video arithmetic

types, eliminating hardware modes

• Branch prediction encoded in instruction, enables zero-

overhead loops

• Parallelism encoded in instruction line

• Conditional execution optional for all instructions

• User-defined, programmable partitioning between pro-

gram and data memory

ON-CHIP SRAM MEMORY

The ADSP-TS101S has 6M bits of on-chip SRAM memory,

divided into three blocks of 2M bits (64K words  32 bits). Each

block—M0, M1, and M2—can store program, data, or both, so

applications can configure memory to suit specific needs. Plac-

ing program instructions and data in different memory blocks,

however, enables the DSP to access data while performing an

instruction fetch.

The DSP’s internal and external memory (Figure 3) is organized

into a unified memory map, which defines the location

(address) of all elements in the system. The memory map is

divided into four memory areas—host space, external memory,

multiprocessor space, and internal memory—and each memory

space, except host memory, is subdivided into smaller memory

spaces.

Each internal memory block connects to one of the 128-bit-

wide internal buses—block M0 to bus MD0, block M1 to bus

MD1, and block M2 to bus MD2—enabling the DSP to perform

three memory transfers in the same cycle. The DSP’s internal

bus architecture provides a total memory bandwidth of

14.4G bytes per second, enabling the core and I/O to access

eight 32-bit data words (256 bits) and four 32-bit instructions

each cycle. The DSP’s flexible memory structure enables:

• DSP core and I/O access of different memory blocks in the

same cycle

• DSP core access of all three memory blocks in parallel—

one instruction and two data accesses

• Programmable partitioning of program and data memory

• Program access of all memory as 32-, 64-, or 128-bit

words—16-bit words with the DAB

• Complete context switch in less than 20 cycles (66 ns)

ADSP-TS101S Datasheet(PDF) 5 Page - Analog Devices

ADSP-TS101S Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL