ADSP-TS101S datasheet(23/48 Pages) AD

23 / 48 page

ADSP-TS101S

Rev. C

Page 23 of 48

May 2009

Table 22. Reference Clocks—System Clock (SCLK) Cycle Time

Parameter

Description

Min

Max

Unit

tSCLK

1, 2, 3, 4

System Clock Cycle Time

tSCLKH

System Clock Cycle High Time

0.4 × tSCLK

0.6 × tSCLK

tSCLKL

System Clock Cycle Low Time

0.4 × tSCLK

0.6 × tSCLK

tSCLKJ

5, 6

System Clock Jitter Tolerance

500

1 For more information, see Table 3 on Page 12.

2 For more information, see Clock Domains on Page 9.

3 LCLK_P and SCLK_P must be connected to the same source.

4 The value of (tSCLK / LCLKRAT2-0) must not violate the specification for tCCLK.

5 Actual input jitter should be combined with ac specifications for accurate timing analysis.

6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

Figure 11. Reference Clocks—System Clock (SCLK) Cycle Time

Table 23. Reference Clocks—Test Clock (TCK) Cycle Time

Parameter

Description

Min

Max

Unit

tTCK

Test Clock (JTAG) Cycle Time

Greater of 30 or tCCLK × 4

tTCKH

Test Clock (JTAG) Cycle High Time

12.5

tTCKL

Test Clock (JTAG) Cycle Low Time

12.5

Figure 12. Reference Clocks—Test Clock (TCK) Cycle Time

Table 24. Power-Up Timing1

Parameter

Min

Max

Unit

Timing Requirement

tVDD_IO

VDD_IO Stable and Within Specification After VDD and VDD_A

Are Stable and Within Specification

1 For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing.

Figure 13. Power-Up Sequencing Timing

SCLK_P

tSCLK

tSCLKH

tSCLKL

tSCLKJ

SCLK_P

tSCLK

tSCLKH

tSCLKL

tSCLKJ

TCK

tTCK

tTCKH

tTCKL

VDD

VDD_A

VDD_IO

tVDD_IO

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