Rev. C

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Page 14 of 48

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May 2009

ADSP-TS101S

MSH

2

O/T (pu

3)

nc

Memory Select Host. MSH is asserted whenever the DSP accesses the host address space

(ADDR31:28

 0b0000). MSH is a decoded memory address pin that changes concurrently with

ADDR pins. In a multiprocessor system, the bus master DSP drives MSH.

BRST2

I/O/T (pu3)

nc

Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading or writing

data associated with consecutive addresses. A slave device can ignore addresses after the first

one and increment an internal address counter after each transfer. For host-to-DSP burst

accesses, the DSP increments the address automatically while BRST is asserted.

inputs are not driven by any source and that dc-biased terminations are not present. It is not necessary to add pull-ups as there are no reliability issues and the worst-case

power consumption for these floating inputs is negligible. Unconnected address pins may require pull-ups or pull-downs to avoid erroneous slave accesses, depending on

the system. Unconnected data pins may be left floating.

Table 6. Pin Definitions—External Port Arbitration

Signal

Type

Term

Description

BR7–0

I/O

epu

Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to arbitrate for

bus mastership. Each DSP drives its own BRx line (corresponding to the value of its ID2–0 inputs)

and monitors all others. In systems with fewer than eight DSPs, set the unused BRx pins high.

ID2–0

1

I (pd

au

Multiprocessor ID. Indicates the DSP’s ID. From the ID, the DSP determines its order in a multi-

processor system. These pins also indicate to the DSP which bus request (BR0–BR7) to assert

when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5,

110 = BR6, or 111 = BR7. ID2–0 must have a constant value during system operation and can

change during reset only.

BM

1

O (pd

2)

au

Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this is a strap

pin. For more information, see Table 16 on Page 19.

BOFF

I

epu

Back Off. A deadlock situation can occur when the host and a DSP try to read from each other’s

bus at the same time. When deadlock occurs, the host can assert BOFF to force the DSP to

relinquish the bus before completing its outstanding transaction, but only if the outstanding

transaction is to host memory space (MSH).

BUSLOCK

3

O/T (pu

2)

nc

Bus Lock Indication. Provides an indication that the current bus master has locked the bus.

HBR

I

epu

Host Bus Request. A host must assert HBR to request control of the DSP’s external bus. When

HBR is asserted in a multiprocessing system, the bus master relinquishes the bus and asserts

HBG once the outstanding transaction is finished.

Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;

Table 5. Pin Definitions—External Port Bus Controls (Continued)

Signal

Type

Term

Description

Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;