Rev. C

|

Page 22 of 48

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May 2009

ADSP-TS101S

For power-up sequencing, power-up reset, and normal reset

(hot reset) timing requirements, refer to Table 26 and Figure 13,

Table 27 and Figure 14, and Table 28, and Figure 15

respectively.

Table 19. AC Asynchronous Signal Specifications (All values in this table are in nanoseconds)

Name

Description

Pulse Width Low (min)

Pulse Width High (min)

Interrupt request input

DMAR3–01

DMA request input

TMR0E

2

Timer 0 expired output

4

 t

FLAG3–0

1, 3

Flag pins input

3

 t

3

 t

TRST

JTAG test reset input

1 ns

Table 20. Reference Clocks—Core Clock (CCLK) Cycle Time

Parameter

Description

Grade = 100 (300 MHz)

Grade = 000 (250 MHz)

Unit

Min

Max

Min

Max

1

Core Clock Cycle Time

3.3

12.5

4.0

12.5

ns

(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 45.

Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time

Table 21. Reference Clocks—Local Clock (LCLK) Cycle Time

Parameter

Description

Min

Max

Unit

1, 2, 3, 4

Local Clock Cycle Time

10

25

ns

Local Clock Cycle High Time

ns

Local Clock Cycle Low Time

ns

5, 6

Local Clock Jitter Tolerance

500

ps

2 For more information, see Clock Domains on Page 9.

Figure 10. Reference Clocks—Local Clock (LCLK) Cycle Time

CCLK

LCLK_P

LCLK_P