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ADSP-TS101S Datasheet(PDF) 8 Page - Analog Devices

Part # ADSP-TS101S
Description  TigerSHARC Embedded Processor
PDF  48 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-TS101S Datasheet(HTML) 8 Page - Analog Devices

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Rev. C
|
Page 8 of 48
|
May 2009
ADSP-TS101S
The DMA controller also supports two-dimensional transfers.
The DMA controller can access and transfer two-dimensional
memory arrays on any DMA transmit or receive channel. These
transfers are implemented with index, count, and modify regis-
ters for both the X and Y dimensions.
The DMA controller performs the following DMA operations:
• External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memory-
mapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.
• Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
• AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
Figure 4. Shared Memory Multiprocessing System
CLKS/REFS
ADDR31–0
DATA63–0
BR1
BR7–2,0
ADDR31–0
DATA63–0
BR0
BR7–1
BMS
CONTROL
ADSP-TS101 #0
CONTROL
ADSP-TS101 #1
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
RESET
RESET
ID2–0
CLKS/REFS
LCLK_P
S/LCLK_N
VREF
SCLK_P
LCLKRAT2–0
SCLKFREQ
000
CLOCK
REFERENCE
VOLTAGE
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
MS1–0
ACK
ID2–0
001
HBG
HBR
CS
WE
WRH/L
SDRAM
MEMORY
(OPTIONAL)
MSSD
FLYBY
IOEN
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
MSH
DMAR3–0
DPA
BOFF
CPA
BRST
LINK
DEVICES
(4 MAX)
(OPTIONAL)
LXCLKIN
LXDIR
LXDAT7–0
LXCLKOUT
TMR0E
BM
CONTROLIMP2–0
LINK
IRQ3–0
FLAG3–0
LINK
RESET
BUSLOCK
CLOCK
DS2–0



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