DS2154 datasheet(33/87 Pages) DALLAS

33 / 87 page

DS2154

33 of 87

RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)

(MSB)

(LSB)

TESF

TESE

JALT

RESF

RESE

CRCRC

FASRC

CASRC

SYMBOL

POSITION

NAME AND DESCRIPTION

TESF

RIR.7

Transmit Side Elastic Store Full. Set when the transmit side

elastic store buffer fills and a frame is deleted.

TESE

RIR.6

Transmit Side Elastic Store Empty. Set when the transmit side

elastic store buffer empties and a frame is repeated.

JALT

RIR.5

Jitter Attenuator Limit Trip. Set when the jitter attenuator

FIFO reaches to within 4 bits of its limit; useful for debugging

jitter attenuation operation.

RESF

RIR.4

Receive Side Elastic Store Full. Set when the receive side

elastic store buffer fills and a frame is deleted.

RESE

RIR.3

Receive Side Elastic Store Empty. Set when the receive side

elastic store buffer empties and a frame is repeated.

CRCRC

RIR.2

CRC Resync Criteria Met. Set when 915/1000 code words are

received in error.

FASRC

RIR.1

FAS Resync Criteria Met. Set when 3 consecutive FAS words

are received in error.

CASRC

RIR.0

CAS Resync Criteria Met. Set when 2 consecutive CAS MF

alignment words are received in error.

DS2154 Datasheet(PDF) 33 Page - Dallas Semiconductor

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